Micron Technology Incorporated

Other

Chris Bueb

Poorna Kale

Sean Stephen Eilert

Daniele Balluchi

Graziano Mirichigni

Emanuele Confalonieri

Tommaso Zerilli

Raffaele Bufano

Sandra Lospalluti

Todd Legler

Marco Gibilaro

Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory

Subject matter disclosed herein relates to a memory device and a method of operating same.

Signal line to indicate program-fail in memory

A method and a memory device are provided for accessing a storage location. The method includes storing an extended address value in a register in a non-volatile memory device. The method further includes subsequently receiving multiple addresses and combining the stored extended address value with each of the multiple received addresses to produce multiple combined addresses. The method further includes accessing multiple storage locations within the non-volatile memory device based, at least in part, on the multiple combined addresses.

Enhanced addressability for serial non-volatile memory

Example embodiments for providing enhanced addressability for a serial flash memory device may comprise providing an extended addressing mode to enable access to a larger range of memory locations.

Extended address mode for serial flash memory

A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.

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Folsom, CA, United States of America

Chris Bueb