Intersil Americas Inc.

Harris Corporation

Intersil Corporation

Chris A McCarty

John T Gasner

Michael D Church

Paul E Bakeman, Jr

David A Decrosta

Sameer D Parab

Robert Lomenick

Stephen J Gaul

Jack H Linn

Leonel Ernesto Enriquez

Robert T Fuller

George S Bajor

Donald Frank Hemmenway

Joseph A Czagas

Robert Lomenic

Paul E Bakeman

Robert L Lomenick

Paul E Bakeman Jr

A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Active area bonding compatible high current structures

A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for same

To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor

In a method of etching a thin film resistor material, such as NiCr or CrSi, and of producing a thin film resistor, a non-photoresist hard mask is deposited on an exposed surface of thin film resistor material, a delineated portion of the hard mask is etched with a hydrogen peroxide etchant that does not affect the thin film resistor material to expose the material therebeneath, and the exposed thin film resistor material is etched with a second etchant that does not affect the hard mask. The second etchant may be sulfuric acid heated to greater than 125.degree. C. for NiCr or a mixture of phosphoric acid, nitric acid and hydrofluoric acid for CrSi. The hard mask preferably comprises TiW.

Direct etch for thin film resistor using a hard mask

Creation of structural defects in a trench-isolated island structure is obviated by protecting the bottom of the trench pattern during etching of the hard mask surface oxide. A layer of photoresist is non-selectively deposited on the hard mask oxide layer and in the trench pattern, so that the photoresist buffer layer fills the trench pattern and is formed atop the hard mask oxide layer. The deposited photoresist is controllably flood-irradiated, so as to expose the irradiated photoresist down to a depth in the trench pattern that is at or somewhat deeper than the surface of the hard mask insulating material. The exposed photoresist is then developed, so as to remove the irradiated depth portion of the photoresist lying atop the hard mask oxide layer and partially extending into the trench, thus exposing the hard mask oxide layer, but leaving a sufficient quantity of unexposed photoresist in the trench pattern that provides a surface barrier for the underlying oxide. A wet etch is then non-selectively applied to the hard mask oxide layer, so as to completely remove the hard mask oxide layer from the top surface of the semiconductor islands. Because of the barrier in the bottom of the trench pattern, the oxide etch does not attack the underlying oxide. The undeveloped photoresist is then stripped. Thereafter, when the sidewalls of the trench pattern are oxidized and the trench pattern is filled with material, lattice dislocations are not formed in the islands.

Stress relief technique of removing oxide from surface of

The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.

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Melbourne, FL, United States of America

Chris A McCarty