Sun Microsystems, Inc.

Nvidia Corporation

Other

Samsung Semiconductor Inc.

Samsung Semiconductors

Chris A Malachowsky

Curtis R Priem

David S Rosenthal

Shuen C Chang

Robert J Rocchetti

Bruce McIntyre

Guy Moffat

Thomas P Webber

Rick Silverman

Michael William Malachowsky

Jeffrey Wayne Malachowsky

Sean Jeffrey Treichler

Brad W Simeral

David G Reed

David B Kirk

Hai D Ho

Lawrence A Sladewski

Peter Ross

Circuits, methods, and apparatus incorporate both a wireless physical interface and audio processing unit on a single integrated circuit. The wireless physical interface may include a receiver, transmitter, or a complete transceiver. The audio processing unit is typically in communication with both the wireless interface and one or more wired physical interfaces. The integrated circuit may be as simple as a wireless physical interface and audio processing unit, or it may include other circuits such as graphics processors, networking interfaces, memories, or other circuits.

Integrated wireless transceiver and audio processor

Methods and systems for reducing noise relating to an electronic system are disclosed. The methods and systems determine a noise signature, which characterizes a targeted noise of the electronic system. A cancellation signal is then generated based on this noise signature, so that if the cancellation signal is transmitted, the targeted noise is at least partially reduced.

Noise reduction in electronic systems

A vending machine is disclosed. The vending machine has a selector for a plurality of beverage types and a selector for a plurality of ice types. The vending machine has a first store for storing a supply of the plurality of beverage types and a second store for storing a supply of the plurality of ice types. The vending machine also has a dispenser for dispensing into a container a selected beverage type and a selected ice type.

Method and system for making and vending ice

A system, method and computer program product are provided for marking an article of manufacture. After marking an article of manufacture with a first identifier that describes at least one aspect of the article, such article is further marked with a supplemental identifier that describes the at least one aspect of the article.

System, method and computer program product for marking an article of manufacture with a supplemental identifier

Embodiments of the present invention include a system for stabilizing a rear view image. The system comprises a camera for capturing a rear view image, wherein the rear view image comprises elements located outside of a passenger vehicle and located behind the passenger vehicle. The system further comprises a motion detector for determining a relative movement between two or more objects e.g., the driver's head and an object within the vehicle. The system further includes an electronic image stabilizer for adjusting the rear view image according to the relative movement and a display device for displaying a stabilized rear view image.

System and method for stabilizing a rear view image

Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Memory address and datapath multiplexing

A vending machine. The vending machine has a selector for a plurality of beverage types and a selector for a plurality of ice types. The vending machine has a first store for storing a supply of the plurality of beverage types and a second store for storing a supply of the plurality of ice types. The vending machine also has a dispenser for dispensing into a container a selected beverage type and a selected ice type.

A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.

Method and apparatus for accelerating rendering by coalescing data

A frame buffer including a memory array, circuitry for accessing the array, a plurality of latches each capable of storing a plurality of pixel values equivalent to a large portion of a row of pixels in the array which may be read simultaneously from the array, and circuitry for writing simultaneously to the memory cells of a row of the array the data stored in the latches whereby a row of pixels may be read and written back to the array bus in a minimum time period.

Method and apparatus for increasing the rate of scrolling in a frame

An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Method and apparatus for providing a configurable display memory for

A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Method and apparatus for providing operations affecting a frame buffer

A flow control circuit for a computer system including a first-in first-out buffer including a register for storing a value indicating the number of stages of the FIFO which are available to store data, circuitry for detecting whether an input/output device is able to process data more rapidly than the FIFO is emptied, and circuitry for providing an value greater than the number of stages actually available for storage in the FIFO if the input/output device is able to process data more rapidly than the FIFO is emptied.

Method and apparatus for providing flow control with lying for

An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.

Method and apparatus for allowing computer circuitry to function with

A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Apparatus for selecting frame buffers for display in a double buffered

A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.

Growing community of inventors

Santa Clara, CA, United States of America

Chris A Malachowsky