Marvell International Limited

Choy Hing Li

Chuan-Cheng Cheng

Shuhua Yu

Shiann-Ming Liou

Xin Yi Zhang

Lakhbeer Singh Sidhu

Xin-Yi Zhang

A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Integrated circuit devices with electrostatic discharge (ESD) protection in scribe line regions

Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same

A method comprising applying a first voltage to a first transistor to create a defect in the first transistor, wherein (i) the first voltage is greater than a maximum operational voltage of the first transistor and (ii) the maximum operational voltage does not cause a defect in the first transistor when applied to the first transistor. The method further includes determining whether the first transistor has been programmed, including (i) measuring a first current through the first transistor, (ii) measuring a second current through a second transistor, and (iii) comparing the measured first current to the measured second current, wherein a difference between the measured first current and the measured second current indicates that the first transistor has been programmed.

Stress programming of transistors

A semiconductor wafer with an electrostatic discharge (ESD) protective device is disclosed. The semiconductor wafer includes first and second adjacent semiconductor die regions, a protective device in a scribe line region between the first and second die regions, and at least one metal line on a surface of the first die region, wherein the metal line(s) is/are in electrical communication with the protective device.

Methods for fabricating and testing integrated circuit devices and systems. The integrated circuit device generally includes two semiconductor dies. The first die has little or no I/O or ESD protection, and the second die includes at least one exposed terminal in electrical communication with one or more terminals on the first die, at least one I/O circuit in electrical communication with one or more terminals on the second die, and at least one I/O terminal in electrical communication with the I/O circuit(s). The method of forming an integrated circuit includes aligning at least one of the exposed terminals on the first die with at least one of the exposed terminals on the second die, and forming at least one electrical junction between them such that the exposed terminal(s) on the first die is/are in electrical communication with an I/O circuit and an I/O terminal on the second die. The method of testing a semiconductor die includes placing the semiconductor die into a predetermined position for testing, placing a tester probe tip in contact with a subset of the exposed terminals on the first die, the probe head having an ESD protection structure in electrical communication with the probe tip, and testing the die.

Method of fabricating a device with ESD and I/O protection

Methods for stressing transistors in order to program the transistors and for determining whether such transistors have indeed been programmed are described herein. The novel methods may include initially stressing a transistor by applying to the transistor a voltage greater than operational voltages of the transistor to create defects in the transistor. A current flowing through the transistor may then be measured to determine whether the transistor has been programmed, the measured current indicative of the presence of the defects.

The integrated circuit devices disclosed herein generally include two semiconductor dies. The first die generally has little or no I/O or ESD protection and includes a first plurality of exposed terminals (e.g., bump pads). The second die generally includes (i) a second plurality of exposed terminals, wherein at least one of the second plurality of terminals is in electrical communication with one or more of the first plurality of terminals, (ii) a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with one or more of the second plurality of terminals, and (iii) a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with one or more of the I/O circuits. The present invention advantageously provides the ability to fabricate the second die using different (e.g., less expensive) manufacturing processes than those used to fabricate the first die.

Integrated circuit devices with ESD and I/O protection

Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.

Collector structure for electrostatic discharge protection circuits

An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Growing community of inventors

Saratoga, CA, United States of America

Choy Hing Li