Skhynix Inc.

Hynix Semiconductor Inc.

Choung Ki Song

Chang Hyun Kim

Jeong Jun Lee

Yo Sep Lee

Mun Gyu Son

Se Ho Kim

Seung Yong Lee

Sang Sic Yoon

Byung Kuk Yoon

Yo-Sep Lee

Jung Ho Lim

Myoung Seo Kim

Eui Cheol Lim

Yong Gu Kang

Jae Seung Lee

Chan Gi Gil

Kibong Koo

Ji Eun Jang

Seok Cheol Yoon

Young Do Hur

Gyung Tae Kim

Woo Jae Shin

Il Kon Kim

Woo Yeong Cho

A buffer chip includes a control signal transmission path that transmitting, to a memory chip, control signals transmitted from a memory controller; a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip; a ring oscillator generating a ring oscillator clock; a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times; a reference value storage circuit configured to store a counting value of the counter circuit as a reference value; a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and a code generation circuit configured to generate the delay code by comparing the reference value with the current value.

Buffer chip, and semiconductor package including buffer chip and memory chip

A processing-in-memory (PIM) system includes a host configured to generate a first request for a memory access operation and a second request for an arithmetic operation, a PIM controller configured to generate a first command based on the first request or the second request, a high speed interface configured to generate a second command based on the second request, and a PIM device configured to perform the memory access operation in response to the first command from the PIM controller and to perform the arithmetic operation in response to the second command from the high speed interface.

Processing-in-memory (PIM) device to perform a memory access operation and an arithmetic operation in response to a command from a PIM controller and a high speed interface, respectively

A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Processing-in-memory (PIM) device, controller for controlling the PIM device, and PIM system including the PIM device and the controller

A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.

Semiconductor device including two or more stacked semiconductor structures

An operation method of a memory may include receiving a meta data read command and a first address; reading meta data from memory cells in columns corresponding to the first address and storing the read meta data in a meta data buffer; receiving a normal read command and a second address; reading normal read data from memory cells in columns corresponding to the second address; and outputting the normal read data and a part of the meta data stored in the meta data buffer.

Memory storing meta data and operation method of memory

There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

Method of performing a multiplication and accumulation (MAC) operation in a processing-in- memory (PIM) device

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication/accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Processing-in-memory devices having multiple operation circuits

An arithmetic device includes an activation function (AF) control circuit, a data storage circuit, and an output distribution signal generation circuit. The AF control circuit generates a column address, a data selection signal, and an internal control signal based on an arithmetic result signal during an activation operation. The data storage circuit outputs activation data from a memory cell array that is selected by the column address and a row address. The output distribution signal generation circuit generates an output distribution signal from the activation data based on the data selection signal and the internal control signal.

Arithmetic devices for neural network

A multiplication-and-accumulation (MAC) circuit includes a MAC operator and a data input circuit. The MAC operator selectively performs a MAC arithmetic operation of weight data and vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and constant data. The data input circuit provides the MAC operator with the weight data and the vector data when the MAC operator performs the MAC arithmetic operation and provides the MAC operator with the weight data and the constant data when the MAC operator performs the EWM arithmetic operation.

Multiplication-and-accumulation circuits and processing-in-memory devices having the same

A processing-in-memory (PIM) device includes memory banks, first and second global buffers, multiplying-and-accumulating (MAC) operators, and output circuits. Each memory bank includes a left memory bank providing left weigh data and a right memory bank providing right weigh data. The first global buffer provides left vector data, and the second global buffer provides right vector data. Each MAC operator includes a left MAC operator performing a MAC operation on the left weight data and the left vector data to generate left MAC data and a right MAC operator performing a MAC operation on the right weight data and the right vector data to generate right MAC data. Each output circuit adds the left MAC data to the right MAC data to generate MAC result data and outputs the MAC result data or activation function-processed MAC result data in response to first and second MAC read signals.

Processing-in-memory (PIM) devices

A semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. The semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. The semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.

Semiconductor device and method for performing test

An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit stores a look-up table for an activation function, adjusts a number of logic level combinations of an input distribution signal that correspond to each logic level combination of the output distribution signal, among a plurality of logic level combinations of the output distribution signal, based on an input range of the activation function. The AF circuit selects and outputs the output distribution signal that corresponds to the input distribution signal based on the look-up table. The input range of the activation function is based on a relative number of errors that occur.

A processing-in-memory device includes a data storage region and an arithmetic circuit. The data storage region includes a first memory bank in which first data is divided into a first portion and a second portion and stored, and a second memory bank in which second data is divided into a first portion and a second portion and stored. The arithmetic circuit performs multiplication/accumulation operations on the first data and the second data and outputs final MAC result data.

An electronic system includes a control system configured to transmit an encrypted bit stream, an electronic device configured to extract a security key by decrypting the encrypted bit stream and to compare the security key with a check security key to extract programming data for a programming operation by decrypting the encrypted bit stream when the security key and the check security key are the same as each other.

Electronic devices and electronic systems for transmitting bit stream including programming data

A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.

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Yongin-si, South Korea

Choung Ki Song