Skhynix Inc.

Hynix Semiconductor Inc.

Choung Ki Song

Chang Hyun Kim

Jeong Jun Lee

Yo Sep Lee

Mun Gyu Son

Se Ho Kim

Woo Yeong Cho

Dong Uk Lee

Seung Yong Lee

Sang Sic Yoon

Byung Kuk Yoon

Yo-Sep Lee

Eui Cheol Lim

Myoung Seo Kim

Jung Ho Lim

Yong Gu Kang

Seung Han Oak

Jae Seung Lee

Chan Gi Gil

Kwang Myoung Rho

Kibong Koo

Ji Eun Jang

Seok Cheol Yoon

Gyung Tae Kim

Young Do Hur

Woo Jae Shin

Il Kon Kim

Geon Ko

A memory module includes a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval. The clock driver adjusts the clock delay interval by comparing the phase of the division clock and the phase of a feedback division clock that is generated from the internal clock.

Memory module related to signal integrity of clock

A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

Semiconductor system related to performing an error check scrub operation

An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.

Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package

A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Stacked integrated circuit

A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.

Buffer chip, and semiconductor package including the buffer chip and a memory chip

A stack memory device includes a base chip, and a core chip stacked with the base chip and electrically connected to the base chip. In the present disclosure, the base chip includes a transmission/reception circuit configured to receive write data, a write valid signal, and a transmission write clock signal, a serialization/parallelization circuit configured to receive the write data, based on the write valid signal in synchronization with the transmission write clock signal and to generate a parallelized input packet from the write data, and a data transmission control circuit configured to decode the parallelized input packet to extract first internal data that is stored in the core chip when a write operation is performed on the core chip from the parallelized input packet.

Stack memory devices communicating via packets

A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, first to Lth additional adders, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The first to Lth additional adders are configured to generate and output first to Mth MAC result data. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. Each of the first to Lth additional adders is classified as either a left additional adder or a right additional adder. The left additional adders are configured to transmit a first portion of the first to Mth MAC result data to the left data I/O circuits, and the right additional adders are configured to transmit a second portion of the first to Mth MAC result data to the right data I/O circuits.

Processing-in-memory (PIM) devices

A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. A Uth MAC operator among the first to Lth MAC operators is configured to output one of the first to Mth MAC result data through a Uth left MAC operator among the first to Lth left MAC operators or a Uth right MAC operator among the first to Lth right MAC operators. The PIM device is configured to output the MAC result data outputted through the left MAC operators through the left data I/O circuits, and output the MAC result data outputted through the right MAC operators through the right data I/O circuits.

A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators, a plurality of memory banks, and a plurality of data input/output (I/O) circuits. The plurality of MAC operators is configured to perform a MAC arithmetic operation using weight data of a weight matrix provided by the plurality of memory banks as input data to generate plural sets of MAC result data corresponding to elements of a result matrix. The PIM device is configured to store the weight data of the weight matrix in the memory banks in units of rows of the weight matrix. The PIM device is also configured to sequentially output the plural sets of MAC result data from the PIM device through the plurality of data I/O circuits according to a sequence in which the row number of the result matrix increases.

A buffer chip includes a control signal transmission path that transmitting, to a memory chip, control signals transmitted from a memory controller; a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip; a ring oscillator generating a ring oscillator clock; a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times; a reference value storage circuit configured to store a counting value of the counter circuit as a reference value; a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and a code generation circuit configured to generate the delay code by comparing the reference value with the current value.

Buffer chip, and semiconductor package including buffer chip and memory chip

A processing-in-memory (PIM) system includes a host configured to generate a first request for a memory access operation and a second request for an arithmetic operation, a PIM controller configured to generate a first command based on the first request or the second request, a high speed interface configured to generate a second command based on the second request, and a PIM device configured to perform the memory access operation in response to the first command from the PIM controller and to perform the arithmetic operation in response to the second command from the high speed interface.

Processing-in-memory (PIM) device to perform a memory access operation and an arithmetic operation in response to a command from a PIM controller and a high speed interface, respectively

A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Processing-in-memory (PIM) device, controller for controlling the PIM device, and PIM system including the PIM device and the controller

A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.

Semiconductor device including two or more stacked semiconductor structures

An operation method of a memory may include receiving a meta data read command and a first address; reading meta data from memory cells in columns corresponding to the first address and storing the read meta data in a meta data buffer; receiving a normal read command and a second address; reading normal read data from memory cells in columns corresponding to the second address; and outputting the normal read data and a part of the meta data stored in the meta data buffer.

Memory storing meta data and operation method of memory

There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

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Yongin-si, South Korea

Choung Ki Song