Taiwan Semiconductor Manufacturing Comp. Ltd.

Chou-Kun Lin

Kuo-Nan Yang

Yi-Chuin Tsai

Chung-Hsing Wang

Chien-Ju Chao

Jerry Chang-Jui Kao

Chin-Shen Lin

Po-Hsiang Huang

Yen-Hung Lin

Nitesh Katta

Yi-Tang Lin

Hsien-Hsin Sean Lee

Chi-Yeh Yu

Cheng-Hung Yeh

I-Fan Lin

King-Ho Tam

A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.

Power gating for three dimensional integrated circuits (3DIC)

Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

Cell having shifted boundary and boundary-shift scheme

Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The first device layer comprises one or more first inverter structures including a first input terminal and a first output terminal. A second device layer is formed on the first device layer. The second device layer comprises one or more second inverter structures including a second input terminal and a second output terminal. One or more inter-layer connection structures are formed. The one or more inter-layer connection structures are disposed to electrically connect the first input terminal to the second output terminal and electrically connect the first output terminal to the second input terminal.

Multi-layer semiconductor structures for fabricating inverter chains

A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.

Voltage control of semiconductor integrated circuits

In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.

Electromigration-aware layout generation

A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Power rail for preventing DC electromigration

Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.

An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Channel doping extension beyond cell boundaries

A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

Metal lines for preventing AC electromigration

A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

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Hsin-Chu, Taiwan

Chou-Kun Lin