Lsi Corporation

Cadence Design Systems, Inc.

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Totic Technology Inc.

Choshu Ito

William Loh

Erik Vaclav Chmelar

Jau-Wen Chen

Rajagopalan Parthasarathy

Li Lynn Ooi

Tze Wee Chen

Sergey Vladimirovich Gribok

Barton Quayle

Payman Zarkesh-Ha

Dan Bui

Ken Doniger

Chi Ming Yeung

Embodiments include herein are directed towards a system and method for circuit emulation. Embodiments may include one or more domains of system components, each respective domain comprising one or more processors of the emulation system. Each respective processor may be configured to execute one or more processing jobs according to an instruction set executed by the respective processor. Embodiments may include a system manager module configured to control an emulation associated with a first domain and identify at least one unused pin associated with the first domain. The system manager module may be configured to allow access to the at least one unused pin for a second domain during the emulation of the first design.

System and method for managing serial lanes in a multi-user emulation system

A method and system for designing an integrated circuit layout are disclosed. In one embodiment, the method includes generating a stem cell library with stem cell layouts, wherein each stem cell layout includes an analog core area where a device element resides, and abutment boundaries on left, right, top, and bottom sides of the analog core area. The method also includes mapping device elements in a schematic netlist to the stem cell layouts in the stem cell library. In addition, the method includes placing and routing the mapped device elements to optimize a layout for the schematic netlist.

Method and apparatus for performing layout designs using stem cells

A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.

Methodology for preventing functional failure caused by CDM ESD

Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin and voltage, the margin phase detector determines whether the sample phase is correct.

Dynamic deskew for bang-bang timing recovery in a communication system

Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.

Tap adaptation with a fully unrolled decision feedback equalizer

A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.

Circuit simulation using step response analysis in the frequency domain

Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Semiconductor package having increased resistance to electrostatic discharge

Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

Systems and methods for speculative signal equalization

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

Systems and methods for synchronous, retimed analog to digital conversion

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.

Electrostatic discharge protection circuit employing a micro electro-mechanical systems (MEMS) structure

A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

Circuit protection system

An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.

Analog-to-digital converter having reduced number of activated comparators

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.

Systems and methods for pipelined analog to digital conversion

An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

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San Mateo, CA, United States of America

Choshu Ito