Analog and Power Electronics Corp.

Anpec Electronics Corporation

Analog and Power Electrics Corp.

Chorng-Wei Liaw

Ming-Jang Lin

Wei-Jye Lin

Ching-Hsiang Hsu

Huang-Chung Cheng

Tian-Fure Shiue

Hau-Luen Tien

A contact process for a semiconductor device containing a base region of a first conductivity type formed on a semiconductor substrate comprises formation of a first shallow layer of the first conductivity type on the base region, deposition of an insulator on the first shallow layer, etching the insulator and first shallow layer to form a contact hole, thermally driving the first shallow layer more deeply into said base region, formation of a second shallow layer of a second conductivity type on the base region at the bottom of the contact hole, filling a metal in the contact hole to contact the sidewall of the first shallow layer and the second shallow layer.

Contact process and structure for a semiconductor device

A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.

Power chip set for a switching mode power supply having a device for providing a drive signal to a control unit upon startup

A process for a trench power MOSFET comprises forming a trench on a semiconductor substrate and an oxide and nitride in the trench, etching the oxide and nitride to remain a part of them at the bottom of the trench, and subsequent procedure for the other structure of the trench power MOSFET. Due to the thick insulator formed at the bottom of the trench, the trench power MOSFET is improved by increased voltage endurance and reduced parasitic capacitance, and thereby the cell density is increased.

Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET

A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. Portions of the fourth dielectric layer and the polysilicon layer are removed until the surfaces of the fourth dielectric layer and the polysilicon layer are substantially level with the surface of the base region.

Method of manufacturing trench gate structure

A latch-up controllable insulated gate bipolar transistor is formed with a thyristor structure, which has a first region of a first conductivity type, a second region of a second conductivity type formed on the first region, a third region of the first conductivity type formed on the second region, and a fourth region of the second conductivity type contacting the third region and forming a P-N junction therewith. The first and third regions contact a first and second electrode regions respectively. A first field effect transistor means for controlling conduction between the fourth region and the second region in response to an actuation bias; and a second field effect transistor means between the fourth region and the second electrode region for turning the thyristor off in response to a cutoff bias. The insulated gate bipolar transistor of the present invention are latch-up controllable, of a high voltage withstand and of a lower forward voltage drop simultaneously

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Chorng-Wei Liaw