International Business Machines Corporation

Texas Instruments Corporation

Chorng-Lii Hwang

Toshiaki Kirihata

Seiji Munetoh

Brian L Ji

Louis L Hsu

Louis Lu-Chen Hsu

Dale E Pontius

Gregory J Fredeman

Rajiv V Joshi

Sang Hoo Dhong

John Atkinson Fifield

Bomy A Chen

Li-Kong Wang

Paul Christian Parries

Clarence W Teng

Alvin Wayne Strong

William A Klaasen

Daniel W Storaska

John W Golz

Roger Aime Dufresne

John Zhu

Charles William Griffin

Toshiaki K Kirihata

A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

Destructive-read random access memory system buffered with destructive-read memory cache

An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

System and method for disconnecting a portion of an integrated circuit

A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture

The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.

Pad system for an integrated circuit or device

Method and arrangement for preconditioning in a destructive read memory

A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.

Method and apparatus for resist planarization

Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRC to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRC after a plurality of external random access cycles n(tRC ) when enabling the corresponding internal random access operation n(tRC ). The additional core random access cycle time tRC is achieved at every n clock, where n>tRC /(tRC &minus;tRC ), or at a time defined by the product of tRC and tRC /(tRC &minus;tRC ). The additional core cycle time tRC is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.

Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline

The difficulty of etching noble metals in ferroelectric capacitors is eliminated by a damascene process that employs chemical-mechanical polishing to remove the unwanted material, resulting in a lower electrode formed in an aperture in a dielectric, having a flat central portion and a wall extending from the central portion to the top surface of the surrounding dielectric; and an upper electrode formed in a two-level aperture, so that the upper electrode structure has a flat central portion, a first vertical wall extending from the central portion to a rim surrounding the central portion and extending over the wall of the lower electrode, and a second vertical wall extending from the rim to the top surface of a surrounding dielectric.

Damascene process for forming ferroelectric capacitors

The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.

Structure and method for reliability stressing of dielectrics

A method of improving the dielectric properties of a thin dielectric disposed on a polycrystalline material, a method of forming a capacitor therewith and the capacitor. An electrode (17) having a polycrystalline material surface having voids (23) extending to the surface, preferably silicon, is provided. A layer of an amorphous form of the material (19) having a thickness of from about 20 .ANG. to about 500 .ANG. is formed over the surface with the amorphous layer disposed within the voids. A thin layer of a dielectric (21) is formed over the amorphous layer and, in the fabrication of a capacitor, a layer of electrical conductor (25) is provided which is spaced from the material over the dielectric. A microcontaminant can be disposed between the polycrystalline material surface and the amorphous layer.

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Wappingers Falls, NY, United States of America

Chorng-Lii Hwang