Industrial Technology Research Institute

National Taiwan University

National Science Council

International Business Machines Corporation

Mediatek Corporation

National Central University

Chorng-Kuang Wang

Muh-Tian Shiue

Po-Chiun Huang

Yuh-Diahn Wang

Chih-Feng Wu

Shen-Iuan Liu

An-Yeu Wu

Chau-Chin Su

Kuang-Hu Huang

Wen-Chi Wu

Wei-Chen Wang

Wayne Leung Cheung

Kun-Yin Wang

Thinh Huu Nguyen

Hsi-Han Chiang

Ming-Hwa Hue

Ten-Long Dan

Tao-Yao Chang

Ret-Bean Lee

Hsan-Fong Lin

Jizoo Lin

Lee-Yuang Huang

Chen-Yi Huang

Jin-Jyh Lee

Shuo-Chun Chou

A differential signal correction circuit is disclosed. The differential signal correction circuit may comprise a first single-ended-to-differential converter and a second single-ended-to-differential converter. Each one of the two converters may comprise an input port and two output ports. The converters may be configured to perform a first phase correction for a pair of differential signals and output a first output signal and a second output signal. The first output signal is fed back to the first converter through one of the output ports of the first converter, and the second output signal is fed back to the second converter through one of the output ports of the second converter so as to perform phase correction and amplitude correction for the first output signal and the second output signal.

Differential signal correction circuit

The signal processing apparatus contains a first signal transforming circuit and a second signal transforming circuit. The first signal transforming circuit includes four first coupled lines and two second coupled lines, wherein two ends of each first coupled line are configured to carry a first pair of differential signals respectively, each second coupled line is magnetically coupled to two of the first coupled lines in parallel and comprises two signal ports, to which the two ends of each of the magnetically-coupled first coupled lines are placed symmetrically for transferring a second pair of differential signals. The second signal transforming circuit is configured to convert between the second pairs of differential signals at the signal ports and a third pair of differential signals at connecting ports of the second signal transforming circuit.

Signal processing apparatus

A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.

Joint carrier synchronization and channel equalization method for OFDM systems

An efficient method for calculating the step-sizes for a frequency-domain equalizer of a discrete-multitone communications system using signal power estimation and tone grouping (SPE-TG) while on-line. The SPE-TG method is used to calculate a plurality of subchannel step-sizes which are then stored in a lookup table. When on-line, the method uses signal power estimation to select step sizes for each tone, and uses these step sizes for frequency domain equalization. The SPE-TG method simplifies the calculations necessary for frequency domain equalization, thereby saving significant hardware and/or processing resources. The SPE-TG method is reliable and robust, and does not depend upon assumptions about the line, location, or channel.

On-line step-size calculation using signal power estimation and tone grouping of the frequency-domain equalizer for DMT-based transceiver

A discrete multi-tone (DMT) communication system is provided herein, replacing the conventional inversed discrete Fourier transform (IDFT) and DFT with IDHT (together with the complex-to-real transformation) and a DHT alone respectively at the transmitting end and the receiving end. A DHT-based frequency-domain equalizer (FEQ) at the receiving end equalizes each of the 0-th to (N&#x2212;1)-th DHT subchannels, where N is the number of point of the DHT. Finally, each of the 0-th to subchannels of the DMT system is obtained by combining the k-th and (N-k)-th subchannels of the DHT-based FEQ for k=0, 1, . . . , 

Discrete multi-tone system having DHT-based frequency-domain equalizer

A sampling timing recovering circuit free from being troubled by a frequency error is provided. Such recovering circuit includes a phase locking circuit having a local frequency for processing an incoming signal having a phase, a specific parameter and an input symbol rate and for locking the phase of the incoming signal, and a frequency locking circuit electrically connected to the phase locking circuit for locking the input symbol rate of the incoming signal to enable the phase locking circuit to desiredly process the incoming signal. A method to this effect is also provided and includes the steps of a) processing an incoming signal having a phase, a specific parameter and an input symbol rate to have the phase lockable, b) locking the phase of the incoming signal, and c) locking the input symbol rate of the incoming signal to enable the incoming signal to be predeterminedly processed.

Method and circuit for sampling timing recovery

A digital servo system for a disk drive provides servo information signal demodulation. The system includes a digital demodulator including a burst signal accumulator that accumulates terms according to respective burst timing intervals to produce a digital, quadrature position error signal (PES). The demodulator also can include a dibit burst filter with synchronous dibit sampling preferably implemented as a Hilbert Transform filter. Alternatively, the demodulator does not include a filter and a squarer and, instead, the squarer comprises a sum-and-squarer that sums the squares of odd and even digitized samples. In another embodiment, the system employs a digital demodulator having a digital squarer that removes any phase component of the digitized servo information signal and includes a burst signal accumulator that accumulates the squared terms according to respective burst timing intervals to produce the PES. The demodulator may include a filter comprising a harmonic notch filter. A spilt burst servo pattern for the servo control system is comprised of half-width transitions that can be written in a signal pass of a recording head and therefore has no phase misalignment between adjacent flux patterns.

Digital pes demodulation for a disk drive servo control system using synchronous digital sampling

A simple demodulation circuit having a reduced hardware cost and an increased using flexibility is provided. Such architecture is used in a pulse position modulation for retrieving a data from a received source signal and includes a transformation circuit operating the source signal to produce a quantized data having a plurality of data slots, a slot address detector electrically connected to the transformation circuit for reaching a peak slot address from addresses of the data slots, and a timing recovery decoder electrically connected to the slot address detector for recovering the data through decoding the peak address.

Architecture of non-synchronous open loop demodulation circuit in pulse position modulation

A transceiver has a pulse position modulation (PPM) encoder, automatic gain control (AGC) circuit and timing recovery circuit. The PPM encoder illustratively has a frequency divider, slot selector, and mixer. The frequency divider divides the frequency of a clock signal to which the data of the non-return to zero (NRZ) signal are aligned to produce a half frequency clock signal. The slot selector selects pulses of the clock signal and the half frequency clock signal depending on logic values of the NRZ signal and a control signal to produce first and second slot selected signals. The mixer mixes the first and second slot selected signals to produce a PPM signal of the NRZ signal. The AGC circuit illustratively has a variable gain amplifier, a hysteresis comparator, an event detector, a timer, and a counter. The variable gain amplifier amplifies the PPM signal using a dynamically adjusted gain that depends on an inputted digital control value. The counter increments the inputted digital control value according to a clock signal outputted from the timer to increase the gain. The hysteresis comparator detects a signal level of the amplified PPM signal. The event detector causes the counter to decrease the inputted digital control value if the signal level is outside of a predetermined signal level range. The timing recovery circuit has a frequency track, a slot locked loop and a phase locked loop. The frequency track generates a coarse clock fx having a frequency that depends on a frequency of the PPM signal. The slot locked loop generates a resampling clock signal having a frequency that depends on the course clock fx and having slots locked to slots of the PPM signal. The phase locked loop locks a phase of the coarse clock fx to a phase of the PPM signal.

Pulse position modulation based transceiver architecture with fast acquisition slot-locked-loop

A relay-race FLL/PLL high-speed timing acquisition device according to the invention comprises a transition detector, a voltage controlled oscillator, a loop filter of PLL, a first lowpass filter, a 90.degree. phase shifter, a second lowpass filter, and a plurality of multipliers. In addition, this relay-race FLL/PLL high-speed timing acquisition device is characterized by further comprising a frequency delimiter which includes a highpass filter coupled to a first circuit, a second circuit coupled to the highpass filter, a third lowpass filter coupled to the second circuit, a Schmitt inverter coupled to the third lowpass filter, and a switch member coupled to the Schmitt inverter. The relay-race FLL/PLL high-speed timing acquisition device can obtain stable and high speed timing acquisition by means of the frequency delimiter.

Relay-race FLL/PLL high-speed timing acquisition device

A fully differential, wide-band transconductance-transimpedance amplifier with a tuneable gain is disclosed. The amplifier includes a transconductance stage for generating a current signal from an inputted voltage signal. The amplifier also has a current gain stage for amplifying the current signal generated by the transconductance stage. Additionally, the amplifier includes a transimpedance stage for generating an output voltage signal from the amplified current signal generated in the current gain stage.

Fully differential CMOS transconductance-transimpedance wide-band

A fully differential, wide-band transconductance-transimpedence amplifier with a tuneable gain is disclosed. The amplifier includes a transconductance stage for generating a current signal from an inputted voltage signal. The amplifier also has a current gain stage for amplifying the current signal generated by the transconductance stage. Additionally, the amplifier includes as transimpedance stage for generating an output voltage signal from the amplified current signal generated in the current gain stage.

A time acquisition system is disclosed with dual independent frequency and phase lock loops, each containing a dedicated voltage controlled oscillator (VCO). The frequency lock loop (FLL) outputs a frequency bias signal, used for coarse frequency lock-up, only when the difference frequency between the input signal and the FLL VCO is outside a predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Significantly, the frequency bias signal is equal to zero when the difference frequency between the input signal and the FLL VCO is inside the frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. The phase lock loop (PLL) provides a phase bias signal, used for fine tuning lock-up, when the difference frequency between the input signal and the PLL VCO is inside the predetermined frequency band -.DELTA..omega..sub.L to .DELTA..omega..sub.L. Therefore, there is no interaction between loops during the final phase tuning lock-up.

Time acquisition system with dual-loop for independent frequency phase

The present invention comprises a fully differential non-op-amp based BJT biquad filter. The biquad filter comprises an unity gain follower receiving a positive and a negative differential input signals for generating a positive and a negative differential output signals. The biquad filter further includes a first positive feedback line connecting the positive output signal to the positive input signal and a second positive feedback line connecting the negative output signal to the negative input signal. The first positive feedback line includes a first capacitor connected in series therein and the second positive feedback line includes a second capacitor connected in series therein wherein the first and the second capacitors are of substantially equal capacitance. The unity gain follower further comprises a plurality of bipolar NPN devices and resistors connected between a common higher DC voltage and a common lower DC voltage through a constant DC current emitter. The unity gain follower is a fully differential follower which further comprises an input voltage shifting stage for receiving and shifting the voltage level of the positive and negative input signals. The unity gain follower further includes a transconductance stage for converting the shifted voltages from the input voltage shifting stage to a positive and a negative current outputs. The unity gain follower further includes a cascode stage for receiving and processing the positive and negative current outputs responsive to the bandwidth of the current outputs to generate a positive and a negative cascoded current outputs. The unity gain follower further has a load stage for receiving the cascoded current outputs to generated a positive and a negative loading voltages. The unity gain follower further includes an output voltage shifting stage for receiving and shifting the loading voltages to generate a positive and a negative shifted output voltages. The unity gain follower further includes an output buffer stage for receiving the shifted output voltages from the output voltage shifting stage and generate a positive and a negative output voltages to provide a low output impedance to the biquad filter.

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Taipei, Taiwan

Chorng-Kuang Wang