Globalfoundries Singapore Pte. Ltd.

Chor Shu Cheng

Lulu Peng

Lawrence Selvaraj Susai

Zishan Ali Syed Mohammed

Yong Chau Ng

Handoko Linewih

Chim Seng Seet

Tze Ho Simon Chan

Yudi Setiawan

Xuesong Rao

Siau Ben Chiah

Chao Li

Sean Lian

Chee Kong Leong

Ming Lei

Shu Zhong

Hua Xiao

Xiongfei Yu

Kelvin Tianpeng Guan

Puay San Chia

Gary Chia

Phyllis Shi Ya Lim

Meng Meng Vanessa Chong

Nur Aziz Yosokumoro

Hendro Mario

Kin San Pey

Aison John George

Nuraziz Yosokumoro

Lieyong Yang

A semiconductor device may include: a substrate; a protective region provided over the substrate; and a core structure enclosed by the protective region. The core structure may include a core material etchable by a chemical solution. The protective region may include a protective material resistant to etching by the chemical solution. The core structure may have a first side and a second side opposite to the first side, the first side being closer to the substrate than the second side. The core structure may be narrowest at the first side of the core structure.

Semiconductor devices and methods of fabricating a semiconductor device

A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Thin film based passive devices and methods of forming the same

An inductive device may be provided, including a first winding layer, a second winding layer arranged over the first winding layer and connected to the first winding layer to form a plurality of turns around a first axis, and a magnetic core arranged vertically between the first winding layer and the second winding layer. The magnetic core may include a portion entirely over the first winding layer and entirely under the second winding layer, where this portion may include a magnetic segment and a non-magnetic segment arranged laterally adjacent to each other along the first axis.

Inductive devices and methods of fabricating inductive devices

A semiconductor device is provided. The semiconductor device comprises an inductor in a far back end of line layer and a capacitor adjacent to and electrically coupled with the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via in a first insulating layer A dielectric layer is provided over the first electrode layer. A second electrode layer is provided over the dielectric layer and a metal fill layer is provided over the second electrode layer. The metal fill layer has a top surface at least level with a top surface of the first insulating layer.

Inductor capacitor filter in far back end of line and integration schemes

An inductive device may be provided, including a substrate and an inductive structure arranged over the substrate. The inductive structure may include a bottom metal winding layer; a top metal winding layer arranged further away from the substrate than the bottom metal winding layer; a magnetic core layer arranged between the bottom metal winding layer and the top metal winding layer; a connector arranged to electrically connect the bottom metal winding layer and the top metal winding layer; and a top metal ring element arranged around the top metal winding layer, spaced apart from the top metal winding layer. The inductive device may further include a guard ring element arranged under the top metal ring element and around the magnetic core layer, spaced apart from the magnetic core layer; wherein the guard ring element may include a magnetic material.

Inductive devices and methods of forming inductive devices

A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.

Semiconductor device having a capacitive structure and method of forming the same

Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.

Reliable passivation layers for semiconductor devices

A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Integrated circuit structure with electrical strap and its method of forming

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Singapore, Singapore

Chor Shu Cheng