Samsung Electronics Co., Ltd.

Choong-Keun Kwak

Du-Eung Kim

Woo-Yeong Cho

Beak-Hyung Cho

Byung-Gil Choi

Sang-beom Kang

Yun-Seung Shin

Hyung-Rok Oh

Hyun-Geun Byun

Kwang-Jin Lee

Young-Ho Suh

Sang-jib Han

Gong-Heum Han

Sang-Jib Han

Hyun-Sun Mo

Baek-Hyung Cho

Do-Eung Kim

Hye-Jin Kim

Seung-Keun Lee

Won-Seok Lee

Joon-Min Park

Sung-Bong Kim

Joon-Yong Choi

Bo-Tak Lim

Beak-hyung Cho

Hyou-Youn Nam

Ho-Geun Shin

Soon-moon Jung

Kyeong-Yoon Bae

A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

Memory cell array biasing method and a semiconductor memory device

A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

Magnetic memory device and method of fabricating the same

Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

Phase change memory devices employing cell diodes and methods of fabricating the same

In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

Nonvolatile memory device and related methods of operation

A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

Control of set/reset pulse in response to peripheral temperature in PRAM device

A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

Memory devices and memory systems having the same

A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Phase-change memory device and method of writing a phase-change memory device

Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range

A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

Phase change memory device using multiprogramming method

The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

Layout method of a semiconductor memory device

A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

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Suwon-si, South Korea

Choong-Keun Kwak