Electronics and Telecommunications Research Institute

Choong Heui Chung

Yong Hae Kim

Jin Ho Lee

Yoon Ho Song

Chi Sun Hwang

Choong Yong Sohn

Jae Hyun Moon

Young Wook Ko

Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. Accordingly, a gate metal is formed which includes a multilayered gate metal layer and has an etched corner region, thereby reducing an electric field of the corner to reduce a leakage current of the TFT.

Method of fabricating thin film transistor having multilayer structure and active matrix display device including the thin film transistor

Provided are a low temperature active matrix display device using a plastic substrate and method of fabricating the same. The low temperature active matrix display device includes: a plastic substrate; a reflection layer disposed on the plastic substrate; a buffer layer disposed on the reflection layer; a thin film transistor disposed on the buffer layer in a first region of the plastic substrate; an interlayer dielectric layer disposed on the thin film transistor; a capacitor disposed in a trench formed in a second region of the plastic substrate and having a first electrode connected to a source electrode and a drain electrode of the thin film transistor, the trench extending from the interlayer dielectric layer to the reflection layer; and a display device having one electrode connected to a second electrode of the capacitor. The above-described structure includes photoresist spacers to decrease a leakage current from the TFT, includes a reflector to protect the plastic substrate from deformation due to laser irradiation, and employs a three-dimensional capacitor to increase an aperture ratio.

Low temperature active matrix display device and method of fabricating the same

The present invention relates to a field emission display in which a gate plate having a gate hole and a gate electrode around the gate hole is formed between an anode plate having phosphor and a cathode plate having a field emitter and a control device for controlling field emission current, wherein the field emitter of the cathode plate is constructed to be opposite to the phosphor of the anode plate through the gate hole. According to the present invention, it is possible to significantly reduce the display row/column driving voltage by applying scan and data signals of the field emission display to the control device of each pixel, And the present invention is directed to improve the brightness of the field emission display in such a manner that the electric field necessary for field emission is applied through the gate electrode of the gate plate to freely control the distance between the anode plate and the cathode plate, so that a high voltage can be applied to the anode.

Field emission display having gate plate

A method of forming a buffer dielectric film in a semiconductor device and a method of manufacturing a thin film transistor using the same are disclosed. By forming a buffer dielectric film containing porous silica material having low heat conductivity between the amorphous silicon layer and the substrate to minimize the heat transfer to the substrate and forming the polysilicon active layer using the laser in the state of securing the crystal growth time, polysilicon active layer having a maximized crystal particle size can be formed to improve the charge mobility of the device, in case of crystallizing the amorphous silicon layer by the ELA method, and the length of the SLG (Super Lateral Grain) can be increased to prevent the nucleation phenomenon from being generated at the portion that the crystals meet and thus the moved number of the mask can be minimized and the throughput of the process can be improved, though the interval of the mask pattern is increased, in case of crystallizing the amorphous silicon by the SLS method.

Growing community of inventors

Daejeon, South Korea

Choong Heui Chung