Samsung Electronics Co., Ltd.

Choong-Bin Lim

Sang-Jun Mun

Jong-Ryun Choi

Ji-hun Oh

Se-Hoon Jeon

Yoon-Beom Song

A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.

Duty cycle error accumulation circuit and duty cycle correction circuit having the same

A universal serial bus (USB) device is comprised of a receiver for receiving signals from a USB host through data lines, and a pull-up resistor circuit connecting pull-up resistors to data lines in response to control signals. The pull-up resistor circuit selectively connects a plurality of pull-up resistors with a data line in response to control signals. The pull-up resistor circuit controls a number of the plurality of pull-up resistors connected with the data line to cause a voltage level of the signal to be lower than a threshold voltage when the USB host resets the USB device.

USB device and data processing system having the same

A configuration of a USB device can include: a serial interface engine (SIE) operable as an interface to a USB host; a controller interface operable as an interface to a controller of the USB device; and a buffer section to buffer at least information transferred from the SIE to the controller interface, the buffer section including a plurality of buffers corresponding to a plurality of endpoints, respectively, where respective buffering capacities of the plurality of buffers are allocated to the plurality of endpoints based upon buffer-utilization information.

Device for controlling endpoints of USB device and method of controlling endpoints of USB device

A USB control system includes a first voltage controller, a control switch, a second voltage controller, and a PHY unit. The first voltage controller outputs a first internal voltage from an external voltage and a reference voltage, and the control switch regulates supplying and suspending the external voltage. The second voltage controller outputs a second internal voltage from the reference voltage and the external voltage applied through the control switch, and the PHY unit receives a request from a host using the first or second internal voltage as a voltage source. The power for certain internal blocks is suspended to reduce power consumption in the USB control system during a power-saving mode.

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Yongin-si, South Korea

Choong-Bin Lim