Intel Corporation

Altera Corporation

Choon Yip Soo

Robert S Chappell

Ho-Seop Kim

Srikanth T Srinivasan

Si Xing Saw

Markos Papadonikolakis

An electronic network system includes a first transmitter circuit that transmits first bits, a second transmitter circuit that transmits second bits, and a port select circuit. The port select circuit includes a first buffer circuit that stores first words in a first packet of the first bits received from the first transmitter circuit, a second buffer circuit that stores second words in a second packet of the second bits received from the second transmitter circuit, and a multiplexer circuit that receives the first words from the first buffer circuit and the second words from the second buffer circuit. The multiplexer circuit interleaves the second words with the first words in an output signal such that a first one of the second words is provided in the output signal after a first one of the first words and before a second one of the first words.

Network systems and methods for word based arbitration of data

An integrated circuit device includes encryption circuitry to encrypt a data packet and scheduler circuitry to receive the encrypted data packet from the encryption circuitry. The scheduler circuitry monitors a duration of time associated with egress of the encrypted data packet, holds the encrypted data packet until the duration of time matches a threshold duration of time, and transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.

Systems and methods for communicating encrypted time-related data

An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.

Method and apparatus for store dependence prediction

A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.

Store address prediction for memory disambiguation in a processing device

Techniques that may be utilized in various computing environments are described. In one embodiment, a buffer is configured dynamically, e.g., during runtime. Other embodiments are also disclosed.

Growing community of inventors

Bayan Lepas, Malaysia

Choon Yip Soo