Samsung Electronics Co., Ltd.

Seoul National University

Choon Ki Jang

Il Han Park

Soojung Ryu

Dong-Hoon Yoo

Jeongwook Kim

Dong Kwan Suh

A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

Processor and memory control method for allocating instructions to a cache and a scratch pad memory

Processor including a cache and a scratch pad memory and memory control method thereof

Growing community of inventors

Seoul, South Korea

Choon Ki Jang