Synopsys, Inc.

Choon Haw Leong

John Theodore Stonick

Giacomino Bollati

David Andrew Yokoyama-Martin

Skye Wolfer

Cuneyt Demirdag

Edoardo Contini

Zhenchang Du

Alberto Minuti

Phase detector circuitry includes first mixer circuitry configured to receive a first clock signal and a second clock signal. The first mixer circuitry includes a first plurality of transistors. The first plurality of transistors includes first transistors, second transistors, and an output transistor. The first transistors receive the first clock signal, and the second transistors receive the second clock signal. The first output transistor outputs a first output signal. The first output signal corresponds to a first phase difference between the first clock signal and the second clock signal.

Phase detection circuitry for high-frequency phase error detection

A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.

Phase mismatch detection for a multiphase system

A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.

Clock and data recovery using closed-loop clock alignment and duplicate sampling clock

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Portland, OR, United States of America

Choon Haw Leong