Fairchild Semiconductor Corporation

Trinno Technology Co., Ltd.

Chongman Yun

Joseph Andrew Yedinak

Christopher Lawrence Rexer

Praveen Muraleedharan Shenoy

Richard L Woodin

Jaegil Lee

Kwanghoon Oh

Jin Young Jung

Praveen Muralheedaran Shenoy

Kwang Hoon Oh

Soo Seong Kim

Hamza Yilmaz

Junyoung Choi

Dwayne S Reichl

Hocheol Jang

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching

Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region.

Power semiconductor device with reduced loss and manufacturing method the same

In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.

Superjunction structures for power devices

In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Superjunction structures for power devices and methods of manufacture

An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.

Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device

A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.

A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.

Growing community of inventors

Seoul, South Korea

Chongman Yun