Ultratera Corporation

Apack Technologies Inc.

S & S Technology Corporation

Other

United Test Center Inc.

Chong-Ren Maa

Ming-Sung Tsai

Wan-Kuo Chih

Albert Lin

Jin-Chyuan Biar

Makoto Nakamura

Hong-Ming Lin

Sam Chiang

Kuo-Teh Ho

Cheng-Hui Lee

Toshikazu Oda

Sunao Meguro

A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.

Method of manufacturing solder mask of printed circuit board

A printed circuit board having a permanent solder mask includes a substrate made of a glassfiber reinforced epoxy resin material. The top and bottom surfaces of the substrate are disposed thereon a conductive pattern respectively. An epoxy resin solder mask is coated on each surface of the substrate in such a way that the conductive pattern is divided into a sheltered portion covered by the solder mask and an unsheltered portion exposed outside. The solder mask also has an even and smooth outer surface with a micro-roughness ranging between 0.5 &#x3bc;m&#x2dc;10 &#x3bc;m and an optimum thickness ranging between 2 &#x3bc;m&#x2dc;200 &#x3bc;m.

Printed circuit board having permanent solder mask

A printed circuit board having a permanent solder mask includes a substrate made of a glassfiber reinforced epoxy resin material. The top and bottom surfaces of the substrate are disposed thereon a conductive pattern respectively. An epoxy resin solder mask is coated on each surface of the substrate in such a way that the conductive pattern is divided into a sheltered portion covered by the solder mask and an unsheltered portion exposed outside. The solder mask also has an even and smooth outer surface with a micro-roughness ranging between 0.5 &mgr;m&tilde;10 &mgr;m and an optimum thickness ranging between 2 &mgr;m&tilde;200 &mgr;m.

One or more through holes are formed by a process in a printed circuit board substrate formed of a resinous dielectric sheet and a conductive layer covering one surface of the dielectric sheet. The process involves the forming by laser one or more cavities on other surface of the dielectric sheet such that the cavities penetrate only the dielectric sheet, without penetrating the conductive layer. Both surfaces of the dielectric sheet are coated with a liquid photoresist layer such that the cavities are filled with the photoresist. A plurality of small areas are formed by photolithography on the surface which is covered with the conductive layer. The small areas are corresponding in location and shape to the cavities which may be of any shape. The small areas are stripped of the conductive, layer by etching before the cavities are stripped of the photoresist. The through holes are thus formed in the small areas defined by the cavities.

Process for forming through holes in substrate of printed circuit board

Method for manufacturing solder mask of printed circuit board

A packaging method for integrated circuit device, which is fit to apply flip chip bonding technique to a leadframe-type chip carrier. The packaging method will not increase the difficulty in assembly of the integrated circuit chip with the leadframe and is able to ensure that the integrated circuit chip be assembled with the lead fingers of the leadframe without false soldering. Also, the packaging method can achieve less inductance of the transmission line and faster transmission speed. In addition, the cost required of the packaging method can be much lower than that for the organic or ceramic base board.

Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method

A hole is generated in a substrate. A chip is connected to the substrate by using the chip receiving area of the substrate by using flip chip assembly. The hole is aligned to the chip receiving area of the substrate. Then, a underfill process is performed such that the space between the chip and the substrate will be encapsulated using liquid capsulated material. The liquid capsulated material is injected into the hole from the back side surface of the substrate to the front side surface of the substrate.

Method for improving the reliability of underfill process for a chip

A chip scale packaging method is used to package a single-sided substrate and one or more semiconductor chips. The nonconductive surface of the substrate is provided with one or more chip-implanting adhesive areas by stenciling. The adhesive areas are provided with one or more through holes. The chips are implanted in the adhesive areas of the substrate such that the active surface of each chip is in contact with the adhesive area, and that the bonding pads of the active surface of the chip are corresponding in location to the through holes. Upon completion of the chip implantation, the substrate and the implanted chips are heated under pressure before the bonding pads are connected with the conductive surface of the substrate by a plurality of metal bonding wires. The chips and the through holes are subsequently provided with a passivation layer. Finally, the conductive surface of the substrate is implanted with a plurality of spherical bonding points in a grid array fashion.

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Taipei, Taiwan

Chong-Ren Maa