Seiko Epson Corporation

Lovoltech, Incorporated

Qspeed Semiconductor Inc.

Other

S-mos Systems, Inc.

Seiko Epson Corporation of Tokyo Japan

Chong Ming Lin

Tatao Chuang

Tran Long

Hy Hoang

Ho Dai Truong

Ho Yuan Yu

Raymond J Werner

Le Trong Nguyen

Wai-Yan Ho

Jay Denning

An exemplary microelectronic device is made up of two or more functional units, which are all disposed on a single chip, or die. The functional units on the die do not all need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention rapidly turns on and off the functional units of the microelectronic device as required by a program being executed. This power down can be achieved by turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units. This results in a very significant reduction in power consumption and corresponding heat dissipation by the microelectronic device as compared to the conventional approach of keeping all functional units operational all of the time.

Selective power-down for high performance CPU/system

A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Programmable junction field effect transistor and method for programming same

A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock generator with programmable non-overlapping-clock-edge capability

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Method for manufacturing a power bus on a chip

A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units interrupting the supply of power to the functional units, or deactivating input signals to the functional units. The operation of the present invention results in a very significant reduction in power consumption and corresponding heat dissipation by the microelectronic device as compared to the conventional approach of keeping all functional units operational all of the time.

An etched substrate structure is augmented by conductive material to provide enhanced electrical and/or thermal performance. A semiconductor device substrate comprising active regions defined on a top surface is masked and etched to define a pattern of blind features in a bottom surface of the substrate. A conductive material is then deposited on the surface of the blind features. The replacement of semiconductor material with the conductive material lowers the resistance between the active elements on the top surface and the bottom surface. The blind features may be placed in proximity to parasitic bipolar transistors in order to increase immunity to latchup. During wafer processing, a pattern of grooves aligned opposite to a scribe street pattern may be etched on the wafer back side in order to facilitate the separation of individual devices.

Structure and method for enhanced performance in semiconductor substrates

A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program. The computer program logic includes means for enabling the processor to receive a plurality of source code instructions, to convert each of the source code instructions into one or more machine code instructions, to generate monitoring information corresponding to each of the machine code instructions, and to enable the microprocessor to output the machine code instructions and the corresponding monitoring information. The monitoring information indicates which of a plurality of functional units of a microprocessor or a microelectronic device are to be selectively activated for executing each of the machine code instructions.

Programmable junction field effect transistor and method for programming the same

A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

Electrostatic discharge protection device for integrated circuits

Computer program product for defining slits in a bus on a chip

A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units. The operation of the present invention results in a very significant reduction in power consumption and corresponding heat dissipation by the microelectronic device as compared to the conventional approach of keeping all functional units operational all of the time.

Growing community of inventors

Sunnyvale, CA, United States of America

Chong Ming Lin