Texas Instruments Corporation

National Semiconductor Corporation

Chong Han Lim

Lee Han Meng@Eugene Lee

Anis Fauzi Bin Abdul Aziz

Wei Fen Sueann Lim

Yee Gin Tea

You Chye How

Siew Kee Lee

Heng Wai Seng

Chee Keong Low

In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.

Semiconductor packages with roughened conductive components

A method of making semiconductor packages includes providing a first lead frame having a first plurality of semiconductor dies arranged along a first longitudinal axis, each of the first plurality of semiconductor dies having a first number of metal contacts; providing a second lead frame having a second plurality of semiconductor dies arranged along a second longitudinal axis, each of the second plurality of semiconductor dies having a second number of metal contacts, the second number of metal contacts different than the first number of metal contacts; and covering the first plurality of semiconductor dies in a first mold using a common semiconductor die cavity; covering the second plurality of semiconductor dies in a second mold using the common semiconductor die cavity.

Universal semiconductor package molds

Roughened conductive components

A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.

Cutting a leadframe assembly with a plurality of punching tools

An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

Integrated circuit package having an IC die between top and bottom leadframes

In a method of testing an IC, short circuits between adjacent I/Os are tested by grounding alternate rows in one step, and alternate columns in another step, and, if necessary including a third step of testing any inadequately tested I/Os by identifying inadequately tested I/Os and then testing these. The identifying may include performing an AND operation on the two I/O configurations of the two first steps, the grounded I/Os being defined as logic 0 and the tested I/Os as logic 1. The third step involves grounding all power supply and all ground pins of the IC and testing the remaining I/Os that were inadequately tested in both of the first two steps.

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Kuala Lumpur, Malaysia

Chong Han Lim