Altera Corporation

Chong H Lee

Ramanand Venkata

Rakesh H Patel

Divya Vijayaraghavan

Vinson Chan

Sergey Yuryevich Shumarayev

Ning Xue

Henry Y Lui

Arch Zaliznyak

Wilson Wong

Curt Wortman

Thungoc M Tran

Huy X Ngo

Michael Menghui Zheng

John D Lam

Toan Thanh Nguyen

Binh Ton

Reza Asayesh

John E Turner

Shoujun Wang

Bill W Bereza

Mei Luo

Edward Aung

Malik Kabani

Paul Butler

Tim Tri Hoang

Keith Duwel

Gopi Krishnamurthy

Lana May Chan

Stjepan William Andrasic

Tin H Lai

William W Bereza

Tam Minh Nguyen

Marcel A LeBlanc

Neville Carvalho

Seungmyon Park

John Dung-Ngoc Lam

Thiagaraja Gopalsamy

A configurable multi-protocol transceiver implemented in an integrated circuit ('IC') includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. Configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations.

Multi-protocol configurable transceiver including configurable deskew in an integrated circuit

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit ('LSB') and most significant bit ('MSB') ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Configurable multi-lane scrambler for flexible protocol support

Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery ('CDR') signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Digital phase locked loop circuitry and methods

One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.

Apparatus and methods of dynamic transmit equalization

A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.

Configurable multi-standard device interface

Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device ('PLD') or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits

A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.

Method and system for operating a communication circuit during a low-power state

A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.

Method and system for transitioning a communication circuit to a low-power state

A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Method and system for operating a communication circuit configurable to support one or more data rates

High-speed serial data transceiver circuitry on a programmable logic device ('PLD') includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop ('PLL') circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

Method and system for efficiently transitioning a communication circuit from a low-power state

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San Ramon, CA, United States of America

Chong H Lee