Advanced Micro Devices Corporation

Chong Chang Lin

Harand Gaspar

Rizwan M Farooq

Melissa D Cooper

Ehab F Barsoum

A method and arrangement is provided for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch. The method includes writing, via the memory interface bus and on a per-bit basis, a first prescribed logic pattern to a prescribed region of the memory to check for one of a bus short to ground and a short between adjacent pins of the memory. The first prescribed logic pattern is read to verify operation of the prescribed region of the memory. The method includes writing, via the memory interface bus and on a per-bit basis, a second prescribed logic pattern, complementary to the first prescribed logic pattern, to a prescribed region of the memory to check for one of a bus short to power and a short between adjacent pins of the memory. The second prescribed logic pattern is read to verify operation of the prescribed region of the memory.

Arrangement for verifying that memory external to a network switch and the memory interface are free of defects

An arrangement for testing flow control logic in a network device such as a network switch includes a traffic generator configured for transmitting pause frames having prescribed pause values. The network device is configured for continuously transmitting data frames on a network medium. The traffic generator is configured for outputting a first pause frame to the network device that specifies a first pause interval on the order of ten minutes, followed by outputting during the first pause interval a second pause frame specifying a second pause interval substantially less than the first pause interval, for example on the order of ten seconds. The traffic generator is configured for measuring a time interval between transmission of the first pause frame and reception of subsequent data frames from the network device for evaluation of the flow control logic. Hence, the traffic generator can determine whether the second pause frame causes the flow control logic to cancel the first pause frame.

Arrangement for testing pause frame response in a network switch

An apparatus is configured for testing a light emitting diode interface. The apparatus includes an integrated network device having a configuration register and logic for generating LED outputs based on detected network events and stored configuration register values. A light emitting diode is associated with the register. A processor is configured to send a signal to the integrated network device to set the configuration register to cause operation of the light emitting diode independent of network events. Hence, a light emitting diode interface of an integrated network device such as a network switch can be tested without sending data packets to the network device.

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San Jose, CA, United States of America

Chong Chang Lin