Qualcomm Incorporated

Chock Hing Gan

Ming Cai

Giridhar Nallapati

Pr Chidambaram

Samit Sengupta

Benjamin Bowers

Gregory Christopher Burda

William Robert Flederbach

James W Hayward

Charanya Gopal

Robert J Bucki

Matthew D Youngblood

Haining S Yang

Bin Yang

Zhongze Wang

Ravi Mahendra Todi

John Jianhong Zhu

Da Yang

Pratyush Kamal

Prayag Bhanubhai Patel

Foua Vang

Jihong Choi

Beom-Mo Han

P R Chidambaram

Chethan Swamynathan

Benjamin John Bowers

Prayag B Patel

A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

System and method of varying gate lengths of multiple cores

In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Semiconductor device having high mobility channel

A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Method and apparatus for a diffusion bridged cell library

An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.

Standard cell architecture using double poly patterning for multi VT devices

An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior

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Chock Hing Gan