Samsung Electronics Co., Ltd.

Cho Eun Lee

Dong Suk Shin

Hyun Jung Lee

Seok Hoon Kim

Seung Hun Lee

Gyeom Kim

Sun Jung Kim

Jin Bum Kim

Jeong Ho Yoo

Min-Hee Choi

Dong Chan Suh

Kwan Heum Lee

Sung Uk Jang

Su Jin Jung

Byeong Chan Lee

Nam Kyu Kim

Ji Eon Yoon

Il Gyou Shin

Dong Myoung Kim

Edward Nam Kyu Cho

Tae Jin Park

Ki Hwan Kim

Young Dae Cho

Kang Hun Moon

Jae Myung Choe

Kyung Hee Kim

Yong Uk Jeon

A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

Semiconductor device

A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

Semiconductor device including a shared semiconductor pattern having faceted sidewalls and method for fabricating the same

There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

Semiconductor device and method for fabricating the same

A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

Method of fabricating semiconductor device

A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

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Pocheon-si, South Korea

Cho Eun Lee