Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Chiyoshi Kamada

Takayuki Iwasaki

Nobuyasu Kanekawa

Atsuo Watanabe

Yasuyuki Kojima

Shinichiro Mitani

Minehiro Nemoto

Seigoh Yukutake

Katsuhiro Furukawa

Masatsugu Amishiro

Takayuki Oouchi

Masahiko Nishiuma

Yoichi Tamaki

Kousuke Tsuji

Hiroyuki Takahashi

Norio Nakazato

Kenji Nagai

Takashi Harada

Kazutaka Masuzawa

Kiyoshi Hayashi

Kazuhiro Yoshihara

Motoo Suwa

Jun Kumazawa

A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Isolator and a modem device using the isolator

The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrateto form a bipolar transistor having a large current capacity.

Semiconductor device and method for fabricating the same

The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate to form a bipolar transistor having a large current capacity.

An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.

A semiconductor device is fabricated by forming first metal balls on electrode pads of a semiconductor chip. The first metal balls each can have a sharp tipped anchor. All of the anchors simultaneously flattened slightly only to the extent of equalizing the height thereof. The first metal balls are bonded to electrodes formed on a substrate with wirings by embedding the anchors into the electrodes. Alternatively, second metal balls can be formed on the electrodes which are then flattened to equalize the height thereof. The first metal balls, either with or without the anchors, are bonded to the second metal balls. The first and second metal balls are preferably heated during the bonding step to soften the second metal balls.

Semiconductor integrated circuit device and fabrication method thereof

For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.

Semiconductor integrated device having parallel signal lines

A high frequency transmission line structure has a reference potential plane conductor layer, a plurality of strip line conductors, a dielectric material layer interposed between the reference potential plane conductor layer and the strip line conductors and a shielding conductor unit provided between adjacent two strip line conductors. The shielding conductor unit includes first and second slender conductor portions extending substantially in a direction parallel with a lengthwise direction of the strip line conductors and connected to be integral with each other at their first ends. The second ends of the first and second slender conductor portions being electrically connected with the reference potential plane conductor layer.

High frequency signal transmission line structure having shielding

A packaged semiconductor device has a package, a semiconductor IC chip disposed in a space formed in the package, a strip conductor buried at a first level in the package for carrying a signal to be coupled to the IC chip, a first reference potential conductor buried at a second level in the package for providing a reference potential for the IC chip and a second reference potential conductor buried at the first level in the package for shielding the strip conductor. A connection conductor such as a bonding wire is provided across the second reference potential conductor for connecting the IC chip with one of the ends of the strip conductor. A dielectric material is provided between the connection conductor and the second reference potential conductor to provide the connection conductor with a characteristic impedance matched with an impedance of a source of the signal the connection conductor carries. The package may have an interconnecting conductor extending to electrically connect the first and second reference potential conductors.

Package having a structure for stabilizing and/or impedance-matching a

In a superhigh speed device driven by GHz band frequencies, a semiconductor integrated circuit device is provided, in which an adjusting impedance is arranged in the inside of a high frequency package accommodating a semiconductor chip to compensate for the mismatching between the characteristic impedance of the package wiring and the terminal impedance of the signal transmission line in the package in order to adjust the input impedance to the characteristic impedance of the signal transmission line.

Growing community of inventors

Kokubunji, Japan

Chiyoshi Kamada