Samsung Electronics Co., Ltd.

Chiweon Yoon

Byunghoon Jeong

Youngmin Jo

Tongsung Kim

Sang-Wan Nam

Daeseok Byeon

Seonkyoo Lee

Donghyuk Chae

Donghun Kwak

Jeongdon Ihm

Kyung-Hwa Kang

Anil Kavala

Jungjune Park

Sung-won Yun

Jihyun Park

Jungyu Lee

Jayang Yoon

Jangwoo Lee

Ji-sang Lee

Yumin Kim

Junha Lee

Kyoungtae Kang

Cheonan Lee

Byungkwan Chun

Junehong Park

Chihyun Kim

Hyeongdo Choi

Eunchan Lee

Chanho Kim

Jintae Kim

Dongku Kang

Jinman Han

Sang-Won Park

Dong-Hun Kwak

Sang-won Shim

Pansuk Kwak

Seungjun Bae

Yoonjae Lee

Bilal Ahmad Janjua

Jung-Soo Kim

Jung-Yun Yun

Daehoon Na

Sangsoo Park

Taehong Kwon

Dongho Shin

Myoung-Won Yoon

Seongjin Kim

Kichang Jang

Joonyoung Kim

Manjae Yang

Sanglok Kim

Hyunsuk Kang

Sung-Won Yun

Doosub Lee

Hyunjin Kwon

Taehyeon Park

Byungjoon Yoo

Eunjin Song

Junghwan Kwak

Hwanseok Ku

Cheolhui Lee

Bilal Ahmad

A data flip-flop circuit includes a flip-flop, a recovery latch and a cut-off transistor. The flip-flop stores a data signal that is input, using a clock signal and a virtual power supply voltage and provides the stored data signal as an output signal at an output node in response to a rising transition of the clock signal. The recovery latch is connected to a power supply voltage and a ground voltage, is connected to the flip-flop at the output node, stores the output signal internally in response to a first transition of a chip enable signal, recovers the stored output signal in response to end of a power gating interval based on the chip enable signal, and provides the recovered output signal to the flip-flop. The cut-off transistor floats the virtual power supply voltage provided to the flip-flop based on a first power gating signal.

Data flip-flop circuit of nonvolatile memory device and nonvolatile memory device including the same

A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

Nonvolatile memory package, storage device including the same, and method of operating thereof

A non-volatile memory device includes a memory cell array including memory cells coupled to word lines, a boost circuit that receives an external power supply voltage and generate a boosted voltage based on the external power supply voltage, a regulator that generates a regulated voltage based on the external power supply voltage, and a control logic that controls word line voltages provided to the word lines. The control logic performs plural program loops in a program operation for the memory cell array. The control logic provides an adjacent word line voltage to an adjacent word line that is adjacent to a selected word line. In a first section of the program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the program loops, the control logic provides the boosted voltage as the adjacent word line voltage.

Non-volatile memory device, storage device having the same and operating method of non-volatile memory device

The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.

Memory device and operating method thereof

A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.

Memory package performing training operation using address-delay mapping and memory system including the same

In a method of operating a memory device, a first operation is performed on a memory block by applying first driving voltages to a plurality of wordlines. After the first operation is completed, a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged is performed. After the first recovery operation is completed, a second operation is performed on the memory block by applying second driving voltages to the plurality of wordlines. In the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline. In the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.

Method of operating memory device and memory device performing the same

A method of generating clock signals includes: receiving a bandgap reference voltage from a bandgap reference circuit; generating a first current having a first curvature characteristic based on the bandgap reference voltage; generating a second current having a second curvature characteristic based on the bandgap reference voltage; generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current; receiving a temperature-variable voltage and a temperature-fixed voltage from a voltage generator; generating an offset current based on the temperature-variable voltage and the temperature-fixed voltage; generating a reference current by adding the first CTAT current to the offset current; and generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.

Clock signal generator and operating method thereof

A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

Voltage generation circuit and semiconductor memory device including the same

Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.

Nonvolatile memory device and memory system including the same

A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.

ZQ calibration circuit for multiple interfaces

A memory device includes a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array including a plurality of memory cells, and a peripheral circuit region under the memory cell array region, wherein the memory cell array region and the peripheral circuit region are electrically connected by through vias, the peripheral circuit region includes a voltage generator configured to generate an operating voltage to apply to the word lines, the voltage generator includes a pumping capacitor unit configured to charge and pump a voltage based on a clock signal, and a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller includes a clock driver configured to apply a clock signal to the pumping capacitor, and the signal controller is adjacent to the through vias.

Voltage generator and memory device including the same

A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

Memory system including an interface circuit connecting a controller and memory

A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

Data transfer circuits in nonvolatile memory devices and nonvolatile memory devices including the same

A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

Storage device for transmitting data having an embedded command in both directions of a shared channel, and a method of operating the storage device

According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

Nonvolatile memory device and operating method with operational amplifier having feedback path

Growing community of inventors

Seoul, South Korea

Chiweon Yoon