Realtek Semiconductor Inc.

Chiu-Yun Tsai

Fu-Ching Hsu

Chia-Jung Chang

Ming-Tsung Tsai

Chien-Lien Peng

A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.

Data access system, and method for operating a data access system

An circuit includes: a plurality of analog-to-digital converters (ADCs) and a control chip. The control chip is utilized for instructing a target ADC to output audio data of a target channel during a target period, and utilized for instructing remaining ADCs not to output audio data in the target period. Then, the control chip defines data timing of the target channel and other channels based on the data receiving time point of the audio data of the target channel. The plurality of ADCs would process analog audio signals of a plurality of channels and output audio data of the plurality of channels according to an assigned order configured by the control chip to form a serial data signal. The control chip separates the audio data of different channels from the serial data signal according to the data timing of the plurality of channels.

Audio processing circuit supporting multi-channel audio input function

A memory sharing dual-mode network communication device includes a first memory, an OTT module and a PON module. The first memory is divided into an OTT region and a PON region, and the OTT module is used to obtain an OTT service, which includes an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit, and a memory slave controller. The PON module includes a PON processor and a second memory main controller. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request of the PON processor to access the OTT area or the PON area of the first memory through the first memory host controller, and the memory arbitration circuit further determines the priority order of the first access request and the second access request.

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Hsinchu, Taiwan

Chiu-Yun Tsai