Powerchip Semiconductor Corporation

United Microelectronics Corp.

Powerchip Semiconductor Manufacturing Corporation

Powerchip Technology Corporation

Chiu-Tsung Huang

Ko-Hsing Chang

Chih-Wei Hung

Wen-Kuan Yeh

Li-Lun Chi

Lu-Min Liu

Ke-Kung Liao

Jen-Chi Chung

Shou-Wei Hsieh

Hann-Jye Hsu

Hsiang-Hung Chang

Chih-Feng Lin

Su-Yuan Chang

Mao-Teng Hsu

Hsin-Heng Wang

Shih-Siang Lin

Ming-Hui Chen

An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Electrostatic discharge protection device

A resistive random access memory including a substrate, a dielectric layer, and at least one memory cell string is provided. The dielectric layer is disposed on the substrate. The memory cell string includes memory cells and at least one first interconnect structure. The memory cells are vertically and adjacently disposed in the dielectric layer, and each memory cells includes a first conductive line, a second conductive line, and a variable resistance structure. The second conductive line is disposed at one side of the first conductive line, and the top surface of the second conductive line is higher than the top surface of the first conductive line. The variable resistance structure is disposed between the first conductive line and the second conductive line. The variable resistance structures in the vertically adjacent memory cells are isolated from each other. The first interconnect structure is connected to the vertically adjacent first conductive lines.

Resistive random access memory and manufacturing method thereof

An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.

Image sensor and fabrication method thereof

A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.

Non-volatile memory including assist gate

A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by the opening. Thereafter, a second insulating layer is formed on the substrate to fill the opening. The second insulating layer together with the first insulation layer form a third insulating layer. The third insulating layer is patterned to form an isolation layer that exposes the substrate and the buried doped region. The isolation layer extends in a second direction and crosses over the first direction. A semiconductor layer is formed on the substrate to fill the areas on the respective sides of the isolation layer.

Method for forming buried doped region

A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.

Multi-level memory cell

A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.

Multi-level memory cell and fabricating method thereof

A method of manufacturing a semiconductor device. The method comprises steps of providing a substrate having a first metal layer and a second metal layer formed thereon. A first dielectric layer, an etching stop layer having a first opening located above the first metal layer and a second opening located above the second metal layer and a second dielectric layer are formed sequentially. A portion of the first dielectric layer and a portion of the second dielectric layer are removed to form a first trench exposing the first metal layer. A capacitor dielectric layer is formed over the substrate. A third opening is formed in the capacitor dielectric layer. A portion of the second dielectric layer and a portion of the first dielectric layer exposed by the third opening are removed to form an opening. A metal layer is formed to fill out the first trench and the opening.

Method of manufacturing semiconductor device

A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

Non-volatile memory cell and manufacturing method thereof

A silicon-on-insulator device structure having a silicon-on-insulator substrate, a transistor and a control transistor is provided. The transistor and the control transistor are disposed on the silicon-on-insulator substrate. The transistor and the control transistor share a common source region. The drain region of the transistor is electrically connected to the main body of the transistor. By forming of a control transistor between the source terminal and the main body of the transistor and switching the control transistor on or off on demand, the silicon-on-insulator device embodies the advantages of both floating-body effect and body-tied characteristic.

Silicon-on-insulator device structure

Sonos multi-level memory cell

Semiconductor device formed on silicon-on-insulator substrate

Dual-bit nitride read only memory (NROM) cell with parasitic amplifier and method of fabricating and reading the same. A NROM cell comprises a semiconductor substrate with a first well region having a conductive type opposite that of the substrate disposed therein. A second well region having a conductive type opposite to the first well region is disposed in the first well region. A gate dielectric layer is disposed over portions of the second well region, wherein the gate dielectric layer comprises a nitride layer. A conductive layer is disposed on the gate dielectric layer to form a gate. And, a pair of first doped regions having a conductive type opposite to the second well region are symmetrically disposed in the second well region of both sides of the gate, wherein one of the first doped regions, the second well region and the first well region constitute a parasitic current amplifier.

Dual-bit nitride read only memory cell with parasitic amplifier and methods of fabricating and reading the same

A method for reading flash memory cell with SONOS structure is disclosed. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trapping layer, a gate conductive layer on the dielectric layer, and source and drain regions in the substrate adjacent to the gate conductive layer. The flash memory cell with SONOS structure is read by applying a positive voltage to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell.

Method for reading flash memory with silicon-oxide/nitride/oxide-silicon (SONOS) structure

An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N region is formed on the bottom layer. The lower portion of the N region is then adjacent to the P-well, and the upper portion of the N region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Growing community of inventors

Hsinchu, Taiwan

Chiu-Tsung Huang