Novatek Microelectronics Corp.

Chiu-Hung Cheng

Chih-Jen Yen

Chih-Yuan Hsieh

Shu-Wei Chang

Po-Chen Lin

Ting-Chun Lin

Chih-Kai Yu

A gate driver and a method for adjusting output channels thereof are provided. The method includes: setting a target number of the output channels; dividing the output channels into a first channel chain and a second channel chain; enabling a scanning operation of the first channel chain according to a clock signal and counting the clock signal to obtain a counting value; and when the counting value reaching a threshold value, enabling a scanning operation of the second channel chain, wherein the threshold value is determined according to a difference value between the target number and the physical number.

Gate driver and method for adjusting output channels thereof

The present disclosure provides a power saving method for a LCD comprising a plurality of scan lines. The power saving method comprises segregating the scan lines into a plurality of scan line groups; and individually performing a waveform-shaping function on each of the scan-line groups at different time points.

Power saving method and related waveform-shaping circuit

A method and an apparatus for stabilizing output from a Phase Lock Loop (PLL) and the PLL thereof is disclosed. The method mainly relates to enabling the control voltage of a voltage control oscillator VCO in the PLL remained unchanged by means of turning off a charge-discharge current source of a charge pump in a PLL in response to a detected reference signal lower than a default value. Furthermore, the method enables the pulse frequency output from the VCO no exceeding a default tolerant frequency range in a distance from a desired output frequency. Thus, when the reference signal resumes the original frequency, the PLL can quickly lock the phase and the frequency again.

Method and apparatus for stabilizing output frequency of PLL (phase lock loop) and phase lock loop thereof

A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.

Sample-and-hold apparatus and operating method thereof

A voltage-controlled current source (VCCS) is provided. The VCCS controls an output current according to a controlling voltage. The VCCS includes an operational amplifier (OP-amplifier), a transistor, a resistor and a current mirror. The present invention utilizes the characteristics of the OP-amplifier to compensate for the voltage difference between the gate and the source of the transistor so that the resulting terminal voltage on the resistor is equal to the input control voltage. Therefore, the VCCS of the present invention can reduce the factors including process drift, fluctuation in the DC voltage source or the output current that can affect the terminal voltage difference of the resistor and hence the accuracy of the output current.

Voltage-controlled current source

A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Growing community of inventors

Hsinchu, Taiwan

Chiu-Hung Cheng