Texas Instruments Corporation

Chitranjan N Reddy

Roger D Norwood

Masashi Hashimoto

G R Rao

Tadashi Tachibana

Pravin P Patel

Ngai H Hong

A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit lines, and active pull-up circuits for restoring bit lines to a full 1 level. The pull-up circuits are not activated on the dummy cell sides, however, because the power used to restore the dummy cell would be wasted since the dummy cell capacitors are always discharged. The device illustrated uses folded bit lines and multiplexed sense amplifiers; one of two opposite pairs of bit lines is selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. The multiplex circuitry selects one side or the other for sensing, and also couples precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other.

Semiconductor dynamic memory device with decoded active loads

A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.

Self refresh circuitry for dynamic memory

A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.

High speed CMOS clock generator

A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit line halves which are of the folded type. The sense amplifiers are multiplexed so that one of two opposite pairs of bit line halves are selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. Thus, the multiplex circuitry operates not only for selecting one side or the other for sensing, but also for coupling precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other. The active pull-up circuits are activated in both read and write portions of a read-modify-write cycle.

Semiconductor dynamic memory device with multiplexed sense amplifier and

A dynamic MOS read/write memory has a substrate bias generator circuit which includes, in this example, four separate pump circuits. A first of these operates only during power-up to quickly produce the desired back bias; this pump circuit uses a high frequency oscillator and a low impedence drive, and cuts off to save power as soon as the necessary bias is reached. A second generates a smaller sustaining current, using a lower frequency oscillator and higher impedance drive; this functions to compensate for leakage during idle periods. The third and fourth pump circuits are driven by RAS and CAS, so these occur only when needed, and at a rate dependent upon the actual operating condition of the memory.

Substrate bias generator for dynamic RAM having variable pump current

A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output. Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence.

Dynamic memory with high speed nibble mode

A clock circuit for producing a high-level delayed clock output following an input clock employs an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.

High-speed low-power delayed clock generator

In a clock generator circuit for a dynamic RAM or the like it is necessary to boot certain nodes to a value to above the supply voltage in order to provide a high-level gate voltage for output transistors. To prevent excess voltage on the gate oxide of a transistor connected to a booted node, a series transistor is added which has the supply voltage on its gate, so neither transistor will have the full booted voltage across its gate oxide.

Reduction of gate oxide breakdown for booted nodes in MOS integrated

A dynamic read/write memory device constructed in a semiconductor chip of the MOS VLSI type employs an on-chip substrate bias generator which is sequentially clocked by the clocks used in operation of the memory. The impact ionization current associated with each clock operation is thus individually supplied, and when a clock is not used the substrate bias for this clock is not generated.

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Houston, TX, United States of America

Chitranjan N Reddy