Alliance Semiconductor Corporation

Other

Active Optical Networks, Inc.

Active Optical Mems Inc.

Chitranjan N Reddy

Ritu Shrivastava

Ajit K Medhekar

Kenneth A Poteet

Subramani Kengeri

Vipul C Patel

Bharat Sastri

Vlad Joseph Novotny

Michael C Stephens, Jr

Darryl G Walker

Roger D Norwood

Thomas Alexander

Kevin P Quinn

Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Light modulator with integrated drive and control circuitry

MEMS devices monolithically integrated with drive and control circuitry

The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current

A DRAM cell ( ) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines ( ) and bit lines ( ) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer ( ) that extends over a source region ( ). A first interlayer dielectric (ILD) ( ) insulates the word lines ( ) from the bit lines ( ) and a second ILD ( ) insulates the bit lines from a cell capacitor. A capacitor contact hole ( ), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs ( and ) to expose the etch barrier layer ( ) over the source region ( ). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer ( ) over the source region ( ) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region ( ).

DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

A method of manufacturing integrated circuits having single and multiple device modes is described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) having a &ldquo;by n&rdquo; input/output (I/O) configuration is fabricated adjacent to a second SRAM having the same I/O configuration. An interconnect scheme spans a single device scribe line that separates SRAM from SRAM , and carries address, timing, and control signals between the adjacent SRAMs ( and ). In the event single SRAMs of a &ldquo;&times;n&rdquo; configuration are desired, the wafer is sawed along the single device scribe line severing the interconnect scheme . In the event multiple device SRAMs of a &ldquo;&times;2n&rdquo; configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Semiconductor devices having cooperative mode option at assembly stage and method thereof

A flash EPROM array ( ) and method of manufacture is disclosed. Source regions ( ) are shared between the memory cells ( ) of row ( ) pairs, and are isolated from one another in the row direction by isolation regions . Low resistance source conductor members ( ) extend in the row direction and are formed over the source regions ( ) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.

Flash EPROM array with self-aligned source contacts and programmable sector erase architecture

A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Shared memory graphics accelerator system

The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller. The embodiments of the present invention could be implemented with discrete components or could be implemented on a single semiconductor substrate.

High speed/low speed interface with prediction cache

According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.

Apparatus and method of reducing the pre-charge time of bit lines in a random access memory

A sensing circuit (30) for a random access memory (10) is disclosed. A CMOS sense amplifier (32) is coupled between bit line pairs which connected to I/O lines by a passgate (N4/N5). A pair of cross-coupled transistors (N6/N7) activated in synchronism with the passgate (N4/N5) is also disposed between the bit lines. The I/O line pairs each include a pair of cross coupled p-channel transistors (P4/P5). The combined action of the cross-coupled pairs (N6/N7) and (P4/P5) increase the sensing speed of the sensing circuit (30).

Data sense arrangement for random access memory

The present invention provides an apparatus and a method of reducing the time to drive the I/O lines by the sense amplifiers. In one embodiment of the present invention, local sense amplifier segments and associated local I/O lines are provided. The I/O lines are short in length and are connected to the sense amplifiers in the associated sense amplifier segments. The reduction in the length of the local I/O lines reduce the effective RC impedance of the I/O lines. Thus, the local sense amplifiers are smaller and drive the local I/O lines much faster. The present invention further provides global I/O lines connected to the local I/O lines. In a second embodiment of the present invention, the global I/O lines are driven by a second stage amplifier. In a third embodiment of the present invention, one global I/O line is provided for every local I/O line.

High performance random access memory with multiple local I/O lines

A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.

Method of reducing dielectric damage due to charging in the fabrication

A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-ship frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Growing community of inventors

Los Altos Hills, CA, United States of America

Chitranjan N Reddy