Intel Corporation

Chitra Natarajan

Amit Gradstein

Robert G Blankenship

Menachem Adelman

Sridhar Muthrasanallur

David Pardo Keppel

Stanley Steve Kulick

Suneeta Sah

Chyi-Chang Miao

Venkata Krishnan

Anthony-Trung D Nguyen

Regev Shemy

Carl J Beckmann

Varin Udompanyanan

Jeff Wilder

Hrishikesh S Pai

Igor Ermolaev

Examples described herein relate to coalescing one or more messages into a coalesced message and representing one or more fields of the metadata of the one or more messages using one or more codes, wherein at least one of the one or more codes uses fewer bits than that of original metadata fields to compact the metadata fields. In some examples, the metadata includes at least one or more of: a target processing element (PE) number or identifier, message length, operation to perform, target address where to read or write data, source PE number or identifier, initiator address in which to write result data, or message identifier.

Metadata compaction in packet coalescing

Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

Supporting adaptive shared cache management

A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

Size-based interleaving in a packet-based link

Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Memory read/write reordering

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Flushing, NY, United States of America

Chitra Natarajan