Everspin Technologies, Inc.

Motorola Corporation

International Business Machines Corporation

Freescale Semiconductor,inc.

Purdue Research Foundation

Motorlola, Inc.

Chitra K Subramanian

Thomas Andre

Syed M Alam

Joseph J Nahas

Halbert S Lin

Bradley J Garni

James D Hayden

Matthew Ronald Croft

Ghavam G Shahidi

Seiji Munetoh

Sufi Zafar

Olubunmi O Adetutu

Mark A Durlam

Brad John Garni

Javed S Barkatullah

Bich-Yen Nguyen

Jon Michael Slaughter

Ramachandran Muralidhar

Michael Alan Sadd

Dimitri Houssameddine

Akihiro Horibe

Kuniaki Sueoka

Yasuteru Kohda

Dean J Denning

Gerold W Neudeck

Sucharita Madhukar

Arkalgud R Sitaram

Devendra K Sadana

Ning Li

Daniel Joseph Friedman

Karthick Rajamani

Saravanan Sethuraman

Nicholas David Rizzo

Frank Robert Libsch

Hillery C Hunter

Bradley Neal Engel

David L O'Meara

Bruce E White

Arun Paidimarri

Mark F Deherrera

Dietmar Gogl

Venkata K Tavva

Subramoney V Iyer

Asanga H Perera

Daniel T Pham

Mark G Fernandes

Archana Redkar

Anthony Mark Miscione

Thomas W Andre

A multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells positioned above the substrate layer. Each photovoltaic cell has a top contact layer and a bottom contact layer connected in series such that the top contact layer of the first photovoltaic cell is connected to the bottom contact layer of a next photovoltaic cell until the last photovoltaic cell is connected. A different voltage is output between the substrate layer and the top contact layer of each photovoltaic cell. Another multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells stacked vertically above the substrate layer. Each photovoltaic cell comprises an active layer separated from the next photovoltaic cell by an etch stop layer until a last photovoltaic cell is reached. A different voltage is output between the substrate layer and the active layer of each photovoltaic cell.

Photovoltaic cell form ultra-small IOT device with multi-level voltage output

An integrated chemical sensor device includes a chemical sensor comprising at least one transistor and having an external sensing surface electrically coupled to a node of the at least one transistor. There is an initialization circuit connected to the base of the at least one transistor configured to set an operating point for the at least one transistor. There is a temperature sensor control circuit coupled to the chemical sensor circuit. The temperature sensor includes a temperature sensor, an analog-to-digital (A/D) converter coupled to the temperature sensor, and a proportional-to-absolute-temperature (PTAT) circuit configured to generate a PTAT reference voltage for temperature compensation. The temperature sensor control circuit is configured to compensate for a change in temperature of the at least one transistor.

Integrated chemical sensor

Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

Radio frequency identification based integrated computer with hardware accelerator

A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Method and system to improve read reliability in memory devices

A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.

True random number generator

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

System implementation of one-time programmable memories

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Wafer scale testing and initialization of small die chips

A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Delayed write-back in memory

Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

Self-referenced sense amplifier with precharge

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Write verify programming of a memory device

An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.

Self-referenced read with offset current in a memory

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Austin, TX, United States of America

Chitra K Subramanian