Victor Company of Japan, Limited

Hitachi, Ltd.

Nippon Victor Kabushiki Kaisha

Chitoshi Hibino

Harukuni Kobari

Yasuhiro Yamada

Susumu Suzuki

Takao Arai

Takashi Hoshino

Masaharu Kobayashi

Kenji Yoshihara

Shigeru Yamazaki

Atsushi Arimoto

A picture producing apparatus alternately operates in mutually different first and second time periods, so as to make access to picture information at a high speed and process the picture information in real time. In the first time period, the picture producing apparatus arranges the picture information which is transmitted into a predetermined format, detects and corrects error in the picture information and writes the picture information into a first memory, and reads picture data stored in a second memory. On the other hand, in a second time period, the picture producing apparatus reads the picture information stored in the first memory, and writes the picture data of the picture information into the second memory depending on control data of the picture information.

Picture producing apparatus

A random access memory has: upper and lower address limits, an address input responsive to an address counter, a write enable input, a read enable input, a data input bus, and data output bus. The address counter is supplied with a synchronization signal having a frequency determined by the frequency of a variable frequency data source. A signal having first, second and third values, respectively indicative of the address input of the memory being at the upper limit for the memory address, the lower limit for the memory address and between the upper and lower limits, is derived in response to the count in the address counter. First, second and third oscillators respectively derive first, second and third fixed frequencies such that the third frequency is greater than the second frequency and the second frequency is greater than the first frequency. The first, second and third fixed frequencies are coupled to the address counter while the signal has the third, second and first values.

Memory control circuit for removing jitter

A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.

System for defeating erroneous correction in a digital signal

A circuit for protecting a horizontal synchronous signal comprises a horizontal synchronous signal detecting circuit responsive to horizontal synchronous pulses included in a composite synchronous signal of a reproduced PCM signal, first and second horizontal synchronous pulse supplementing or adding circuits and an output switching circuit. The output switching circuit operates so that the first supplementing circuit delivers a first supplementary pulse in the absence of a single pulse of the original horizontal synchronous signal, and the second supplementing circuit produces one or more second supplementary pulses in the absence of a plurality of continuous pulses of the original horizontal synchronous signal. When the circuit returns to a condition in which produced horizontal synchronous pulses are synchronous with the original horizontal synchronous pulses, the time interval between adjacent pulses of the original pulses is detected to see whether the interval is either longer or shorter than a predetermined value. As a result, when a pulse first appeared after the returning point is within the predetermined interval, that pulse is removed so that the number of output horizontal synchronous pulses is correct.

Circuit and method for protecting a horizontal synchronous signal

A double error correcting system is used in a digital signal reproducing apparatus, which is capable of correcting errors in two information vectors (information words) among a plurality of information vectors within one block by use of elements in a small number of correcting matrices and by using a memory device having a small memory capacity. A register is not required for temporarily storing the operational result obtained half-way between a plurality of performed operations. Instead, corrected information vectors are obtained from a memory circuit.

Double error correcting system in digital signal reproducing apparatus

A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for supplying a control signal to the first memory. The first control circuit producing the control signal for controlling the first memory in such a manner that the total memory capacity of the first memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) for use, and the modulated digital signal is written in and further the modulated digital signal thus written in is read out with the order thereof rearranged, interrelatedly with the circulation of addresses through the plurality of divided memory capacity segments while maintaining constant the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments.

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Yokohama, Japan

Chitoshi Hibino