Taiwan Semiconductor Manufacturing Comp. Ltd.

Aiwan Semiconductor Manufacturing Company, Ltd.

Chiting Cheng

Yangsyu Lin

Jonathan Tsung-Yung Chang

Cheng Hung Lee

Hung-Jen Liao

Yen-Huei Chen

Wei-Jer Hsieh

Yu-Hao Hsu

Chien-Kuo Su

Chen-Lin Yang

Fu-An Wu

Shang-Chi Wu

Mahmut Sinangil

Pankaj Aggarwal

Jhon Jhy Liaw

Jung-Ping Yang

Tsung-Yung Chang

Chung-Cheng Chou

Hao-I Yang

Hsin-Hsin Ko

Hidehiro Fujiwara

Wei Min Chan

Chien-Chen Lin

Chia-Chen Kuo

Haruki Mori

Chi-Lung Lee

Chien-Chi Tien

Zhi-Hao Chang

Hsiao Wen Lu

Hau-Tai Shieh

Hong-Chen Cheng

Chien-Yuan Chen

Yi-Tzu Chen

Jui-Che Tsai

Jung-Hsuan Chen

Michael Patrick Clinton

Li-Chun Tien

Chia-En Huang

Jack Liu

Cheng-Hung Lee

Ming-Zhang Kuo

Kun-Hsi Li

Tsung-yung Jonathan Chang

Hektor Huang

Chien Chi Tien

Sang Hoo Dong

Hsiao-Wen Lu

May Chang

Hsiu-Feng Peng

Shu Cheng Huang

Zhi-hao Chang

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Voltage regulator with power rail tracking

A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.

Power detection circuit

In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

Pre-charging bit lines through charge-sharing

A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.

Layout of static random access memory periphery circuit

A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.

Bit line logic circuits and methods

A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

Clock circuit and method of operating the same

Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Configurable memory storage system

A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

Memory macro and method of operating the same

A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

Bit line secondary drive circuit and method

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Taichung, Taiwan

Chiting Cheng