Nanyang Technological University

Delta Electronics Int'l (Singapore) Pte Ltd

Huawei Technologies Co., Limited

Massachusetts Institute of Technology

Globalfoundries Singapore Pte. Ltd.

Chirn Chye Boon

Jack Sheng Kee

Xiang Yi

Kaituo Yang

Junping Zhang

Devrishi Khanna

Lap Chan

Sheng Liu

Eugene A Fitzgerald

Shimon Shilo

Doron Ezri

Dong Liang

Kiat Seng Yeo

Dimitri A Antoniadis

Manh Anh Do

Johnny Kok Wai Chew

Suh Fei Lim

Pilsoon Choi

Sunny Sharma

Dror Regev

Ping Qiu

Zhipeng Liang

Gengen Hu

Dimitri Antoniadis

An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

Apparatus and method for wireless communication

A signal receiving circuit amplifies a radio frequency signal by using a first radio frequency amplifier, outputs a first amplified signal in a same phase, amplifies the radio frequency signal by using a second radio frequency amplifier, and outputs a second amplified signal at an inverse phase. A first mixer mixes a first local oscillator signal with the first amplified signal to obtain a first frequency mixing signal, and a second mixer mixes a second local oscillator signal with the second amplified signal to obtain a second frequency mixing signal, where a phase of the first local oscillator signal is opposite to a phase of the second local oscillator signal. After adding the first frequency mixing signal and the second frequency mixing signal, an output interface outputs the first frequency mixing signal and the second frequency mixing signal.

Signal receiving circuit, signal processing chip, communications device, and signal receiving method

A charge-based charge pump with wide output voltage range is provided. In the charge-based charge pump, the digital logic circuit is configured to receive an up pulse signal and a down pulse signal and output a plurality of switching signals for controlling the first NMOS, the positive hold subcircuit, the first dynamic body-bias generator, the positive charge transfer subcircuit, the first static body-bias generator, the first PMOS, the negative hold subcircuit, the second dynamic body-bias generator, the negative charge transfer subcircuit and the second static body-bias generator electrically connected therewith, so as to allow the output voltage to range from &#x2212;0.84&#xb7;VDD to 1.82&#xb7;VDD. The charge-based charge pump is triggered by the up or down pulse signal or works in a default state, and the top plate and the bottom plate of the pump capacitor are electrically connected to different node and terminal according to the plurality of switching signals.

Charge-based charge pump with wide output voltage range

A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.

Low noise amplifier

A time-to-digital converter is provided. The time-to-digital converter comprises an oscillator controller, an invertible oscillator and a measurement circuit. The oscillator controller receives a start signal and a stop signal and outputs a mode signal. The invertible oscillator is electrically connected with the oscillator controller for receiving the mode signal. The oscillation direction of the invertible oscillator is inverted according to the mode signal, and the invertible oscillator outputs plural delay signals. The measurement circuit is electrically connected with the invertible oscillator for receiving the plural delay signals. The measurement circuit receives a sampling signal, samples the plural delay signals in accordance with the sampling signal, and outputs an output signal.

Time-to-digital converter

The communication receiver comprises a mixer being configured to mix the communication signal with a periodic mixing signal having a mixing frequency fto obtain a mixed communication signal, wherein the mixed communication signal comprises a first frequency spectrum portion comprising the spectral region of interest being situated around a frequency f+fand a second frequency spectrum portion comprising the spectral range of interest being situated around f&#x2212;f; a first demodulator being configured to demodulate a first frequency channel of the plurality of frequency channels within the spectral range of interest of the first frequency spectrum portion on the basis of a first local oscillator frequency f; and a second demodulator being configured to demodulate a second frequency channel of the plurality of frequency channels within the spectral region of interest of the second frequency spectrum portion on the basis of a second local oscillator frequency f.

Communication receiver and method

An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

Analog-to-digital converter

An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.

Tunable high quality factor inductor

Growing community of inventors

Singapore, Singapore

Chirn Chye Boon