Arm Limited

Chiranjeev Acharya

Sean James Salisbury

Arthur Brian Laughton

Eduard Vardanyan

Premkishore Shivakumar

An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

Chunking for burst read transactions

Routing circuitryis provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulatorsare provided to monitor resource usage for read, atomic and write requests, and issue circuitrycontrols the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.

Regulation for atomic data access requests

Data access routing circuitryis provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitryis provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitryreserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resourcefor handling read requests.

Resource allocation for atomic data access requests

An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

Relative data width indication for read responses routed by an interconnect

Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

Growing community of inventors

Sheffield, United Kingdom

Chiranjeev Acharya