International Business Machines Corporation

Georgia Tech Research Corporation

Chirag Suryakant Patel

Paul Stephen Andry

John Ulrich Knickerbocker

Edmund Juris Sprogis

John Harold Magerlein

James D Meindl

Russell Alan Budd

Muhannad S Bakir

Kevin P Martin

Evan G Colgan

Bing Dang

Lawrence Shungwei Mok

Cornelia K Tsang

Paul Albert Kohl

David Earle Seeger

Luc Gilbert Guerin

Herbert I Stoller

Hollie K Reed

Daniel C Edelstein

Christopher Vincent Jahnes

Peter Alfred Gruber

John Michael Cotte

Duixian Liu

Brian Paul Gaucher

Thomas K Gaylord

Cornelia Kang-I Tsang

Leena Paivikki Buchwalter

Ullrich Richard Pfeiffer

Harvey Charles Hamel

Elias N Glytsis

Punit P Chiniwalla

Samuel McKnight

Stephen M Schultz

Nils Deneke Hoivik

Janusz Grzyb

Guy M Cohen

Philip George Emma

Robert K Montoye

Gareth Geoffrey Hougham

Harm Peter Hofstee

Xiao Hu Liu

Frank Robert Libsch

George Frederick Walker

Benjamin V Fasano

Jon Alfred Casey

Keith Aelwyn Jenkins

Paul Francis Fortier

Raymond R Horton

Brian Richard Sundlof

Michael Wayne Lane

David Hirsch Danovitch

Michelle Leigh Steen

Sherif Ahmed Goma

Sylvain E Ouimet

George A Katopis

Tony Mule′

Tony Mule&prime;

Lie Shan

A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.

Silicon carrier space transformer and temporary chip attach burn-in vehicle for high density connections

Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.

Silicon based optical vias

A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.

Semiconductor device and method of making semiconductor device

Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Techniques for forming solder bump interconnects

A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Silicon carrier structure and method of forming same

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Silicon carrier optoelectronic packaging

A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.

A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.

Chip carrier substrate including capacitor and method for fabrication thereof

A semiconductor device includes a semiconductor chip, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.

A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Method and manufacture of silicon based package and devices manufactured thereby

Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement

Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device

Silicon based package

Growing community of inventors

Peekskill, NY, United States of America

Chirag Suryakant Patel