University of California

Chirag Gupta

Umesh Kumar Mishra

Stacia Keller

Srabanti Chowdhury

Elaheh Ahmadi

Silvia H Chan

Jeonghee Kim

Yusuke Tsukada

Yuuki Enatsu

Anchal Agarwal

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

III-N based material structures, methods, devices and circuit modules based on strain management

An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

Method to achieve active p-type layer/layers in III-nitrtde epitaxial or device structures having buried p-type layers

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

Growing community of inventors

Santa Barbara, CA, United States of America

Chirag Gupta