Qualcomm Incorporated

Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Chirag Gulati

Sei Seung Yoon

Ritu Chaba

Rakesh Kumar Sinha

Lakshmikantha Holla Vakwadi

Venkatasubramanian Narayanan

Rita Zappa

Jitendra Dasani

Stefano Corbani

Ashish Akhilesh

A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

Reconfigurable memory interface circuit to support a built-in memory scan chain

A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Process tolerant current leakage reduction in static random access memory (SRAM)

Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Memory timing circuit

A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.

High frequency pseudo dual port memory

An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Read/write assist for memories

Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

Memory with multiple word line design

A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

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Kota, India

Chirag Gulati