Actrans System Inc.

Silicon Storage Technology, Inc.

Actrans System Incorporation, USA

Other

Chiou-Feng Chen

Der-Tsyr Fan

Prateep Tuntasood

Jung-Chang Lu

Ming-Jer Chen

Caleb Yu-Sheng Cho

Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Process of fabricating flash memory with enhanced program and erase coupling

NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

NAND flash memory with nitride charge storage gates and fabrication process

NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

NAND flash memory with densely packed memory gates and fabrication process

Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Self-aligned split-gate NAND flash memory and fabrication process

Flash memory with enhanced program and erase coupling and process of fabricating the same

Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Flash memory with trench select gate and fabrication process

Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and provide substantially better programming and erase performance than memory cells of the prior art.

Flash memory cells with separated self-aligned select and erase gates, and process of fabrication

Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the shallow and deep diffusion regions of the stack transistor. The memory cell in which the control gate is self-aligned with the floating gate is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, forming shallow and deep diffusion regions along the two edges of the floating gate in the silicon substrate, and forming source and drain regions in the silicon substrate by lightly doped diffusion (LDD) implantation for the select transistors. The memory cell in which the control gate is not self-aligned to the underlying floating gate is formed by patterning the floating gate before the patterning of the control gate and the select gate. The memory cells can be operated in the bit-erasable or byte-erasable EEPROM mode when the deep diffusion region is along one side of the floating gate facing the adjacent select gate, and in page-erasable or sector-erasable flash memory mode when the deep diffusion region along the side of the floating gate opposite the adjacent select transistor.

Memory cell with self-aligned floating gate and separate select gate, and fabrication process

Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Flash memory cell with contactless bit line, and process of fabrication

Nonvolatile memory cell and process in which a thin floating gate is formed with a rounded lateral edge and a thickness on the order of 100-1000 &angst; over a gate oxide in an active area on a silicon substrate. A tunnel oxide is formed adjacent to the rounded edge of the floating gate, and a control gate is formed with a lower portion next to the tunnel oxide and an upper portion overlying the floating gate. In some disclosed embodiments, the upper portion of the control gate completely overlies the floating gate, and in others it only partially overlies it.

Flash memory cell with thin floating gate with rounded side wall, and fabrication process

Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

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Santa Clara, CA, United States of America

Chiou-Feng Chen