Via Technologies, Inc.

Chinyi Chiang

Tse-Hsien Wang

A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of interface signals of a serial ATA external physical layer, essentially comprising a decoder/encoder, a serializer/deserializer, a phase locked loop, at least one transmitter, at least one receiver, and at least one OOB signal detector, encoding various control signals and various status signals, required for the connection between the decoder/encoder and a storage medium controller, into data signals using signals other than a data conversion requirement of 8bits and 10bits, by means of a decoder/encoder, in order for greatly reducing the number of interface signals required for the connection between the external physical layer and a main control chip.

Circuit structure and signal encoding method for a serial ATA external physical layer

A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of interface signals of a serial ATA external physical layer, essentially comprising a decoder/encoder, a serializer/deserializer, a phase locked loop, at least one transmitter, at least one receiver, and at least one OOB signal detector, encoding various control signals and various status signals, required for the connection between the decoder/encoder and a storage medium controller, into data signals using signals other than a data conversion requirement of 8 bits and 10 bits, by the decoder/encoder, in order for greatly reducing the number of interface signals required for the connection between the external physical layer and a main control chip.

A physical layer apparatus compliant for both serial and parallel ATA interfaces is devised. The physical layer apparatus includes a serial ATA physical layer circuit, a channel selection unit and a channel selection controller. The channel selection unit is connected to a media access controller of a host through a first IDE bus. The channel selection unit is further selectively connected to a serial ATA device through the serial ATA physical circuit or connected to a parallel ATA device through second IDE bus. Therefore, the media access controller of the host can selectively access the serial ATA device and the parallel ATA device through the channel selection unit under the control of the channel selection controller.

Physical layer apparatus compliant to serial and parallel ATA interfaces

A serial ATA control circuit is provided. The control circuit includes a plurality of serial ATA controllers, a plurality of port controlling circuits, a plurality of switch devices, and a switch controller. Each of the serial ATA controllers has a memory accessing controller and two transceivers. The serial ATA control circuit is connected to at least one serial ATA device through the port controlling circuits. The a plurality of port controlling circuits are connected to corresponding serial ATA controllers through the plurality of switch devices controlled by the switch controller. The connection path between each port controlling circuit and corresponding serial ATA controller is selected by the switch controller to achieve optimal data transfer rate.

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Taipei, Taiwan

Chinyi Chiang