Advanced Micro Devices Corporation

Ati Technologies Ulc

Chintan S Patel

Vydhyanathan Kalyanasundharam

Benjamin Tsien

Alan Dodson Smith

Alexander J Branover

Eric Christopher Morton

Narendra Kamat

Ganesh Balakrishnan

Guhan Krishnan

Girish Balaiah Aswathaiya

Joe J Sargunaraj

Edgar Munoz

Stephen Victor Kosonocky

Indrani Paul

John J Wuu

Christopher Jude Brennan

John P Petry

Ravindra Nath Bhargava

Tarun Nakra

Greggory D Donley

Bryan P Broussard

Mihir Shaileshbhai Doctor

Andrew William Lueck

Thomas James Gibney

Ashish Jain

Christopher T Weaver

Akhil Arunkumar

Pravesh Gupta

Gregg Donley

Akshay Lahiry

Shang Yang

Jose G Cruz

Vamsi Krishna Alla

Nithesh Kurella Lakshmi Narayanamurthy

Sreenath Thangarajan

The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.

Low power memory state during non-idle processor state

The disclosed computer-implemented method includes detecting a low utilization time period for memory traffic between a cache and memory, selecting from the cache, in response to detecting the low utilization time period, a dirty cache entry based on one or more factors, and writing the dirty cache entry back to the memory during the low utilization time period. Various other methods, systems, and computer-readable media are also disclosed.

Dynamically controlled cache rinsing

The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.

Running average cache hit rate

Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

Dynamic buffer management in multi-client token flow control routers

A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

Last level cache access during non-Cstate self refresh

A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Technique to enable simultaneous use of on-die SRAM as cache and memory

A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

Allocation control for cache

Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Device and method for reducing save-restore latency using address linearization

A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

Dynamic cache bypass for power savings

A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

Mechanism to efficiently rinse memory-side cache of dirty data

A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

Low power cache

A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.

Cache allocation policy

Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.

Cache prefetching with dynamic interleaving configuration modification

A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.

Direct mapping mode for associative cache

Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

Growing community of inventors

Bee Cave, TX, United States of America

Chintan S Patel