Qualcomm Incorporated

Chintalapati Bharath Sai Varma

Santhosh Reddy Akavaram

Prakhar Srivastava

Ravi Kumar Sepuri

Sridhar Anumala

Sai Naresh Gajapaka

Sonali Jabreva

Yogananda Rao Chillariga

Hung Vuong

Vamsi Krishna Sambangi

Radhakrishna Mugada

Sai Jitendra Varma Gadiraju

Khushboo Kumari

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

Host management of write buffer size for flash memory

Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.

Unmapping a write buffer portion for access during a write to a memory device

A device includes a flash interface configured to be coupled to a flash memory device. The device also includes a host controller configured to select an interrupt level that indicates a threshold background operation status of a set of background operation statuses. The host controller is also configured to write the selected interrupt level to a register at the flash memory device to indicate, to the flash memory device, which of the set of background operation statuses are permissible sources of an interrupt from the flash memory device to the host controller.

Enhanced power management of flash memory device

An integrated circuit (IC) device, implemented using chiplets mounted on a substrate, may include a controller and a first plurality of link modules. The first plurality of link modules may be configured to provide data lanes in a multimodule data communication link. The controller may be configured to retrain a failed link module in the first plurality of link modules while one or more other link modules in the first plurality of link modules are active and available for transmitting or receiving data, reconfigure the multimodule data communication link to use a second plurality of link modules that excludes the failed link module and includes fewer link modules than the first plurality of link modules, and reconfigure the multimodule data communication link to use the first plurality of link modules for transmitting or receiving the data after the failed link module has been successfully retrained.

Mechanism to enhance link bandwidth in interconnects

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

Host management of flash memory with shared write buffer

This disclosure provides systems, methods, and devices for memory systems that support exception event handling and reporting. In a first aspect, a method of exception event handling in a flash memory system includes a host memory controller receiving a response from the memory system, the response comprising user data, an indication that an exception event was encountered by the memory system, and information regarding the exception event encountered by the memory system; and transmitting an acknowledgement of receiving the indication that the exception event was encountered by the memory system. Other aspects and features are also claimed and described.

Exception event handling in flash memory system

Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the memory resource utilization of a data storage device that uses nonvolatile memory (NVM) to store data. In some aspects, the data storage device can be provided with multiple write buffers to improve the write throughput of the device. In some aspects, the data storage device can use a utilization array to keep track of the utilization information of each write buffer. In some aspects, the data storage device can repurpose the memory of a write buffer with low utilization to serve an active logical unit which becomes full, thus preserving the function of the write buffer of the active logical unit.

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Hyderabad Telangana, India

Chintalapati Bharath Sai Varma