Palo Alto Research Center Inc.

Chinnwen Shih

Jackson H Ho

Christopher L Chua

David Kirtland Fork

Eugene Michael Chow

Raj B Apte

William S Wong

Jeng Ping Lu

Michael L Chabinyc

Thomas Hantschel

Dirk De Bruyker

Brent Shawhan Krusor

JengPing Lu

JengPing Liu

Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.

Sub-resolution gaps generated by controlled over-etching

Spring structures are subjected to pre-release and post-release annealing to tune their tip height to match a specified target. Post-release annealing increases tip height, and pre-release annealing decreases tip height. The amount of tuning is related to the annealing temperature and/or time. Annealing schedules are determined for a pre-fabricated cache of unreleased spring structures such that finished spring structures having a variety of target heights can be economically produced by releasing/annealing the cache according to associated annealing schedules. Selective annealing is performed using lasers and heat absorbing/reflecting materials. Localized annealing is used to generate various spring structure shapes. Both stress-engineered and strain-engineered spring structures are tuned by annealing.

Release height adjustment of stressy metal devices by annealing before and after release

An apparatus integrating electrostatically actuated MEMS devices and high voltage driver (actuator) electronics on a single substrate, where the driver electronics utilize offset-gate high voltage thin-film transistors (HVTFTs) that facilitate the transmission of high actuating voltages using relatively low control voltages, thereby facilitating the formation of large arrays of electrostatically-actuated MEMS devices. The driver circuit is arranged such that the high actuating voltage is applied to an actuating electrode of the actuated MEMS device and drain electrode of the HVTFT when the HVTFT is turned off, thereby minimizing dielectric breakdown. When the HVTFT is turned on in response to the relatively low control voltage, the high actuating voltage is discharged to ground from the drain (offset) electrode to the source (not offset) electrode.

Integrated driver electronics for MEMS device using high voltage thin film transistors

Growing community of inventors

Santa Clara, CA, United States of America

Chinnwen Shih