Micron Technology Incorporated

Samsung Electronics Co., Ltd.

Western Digital Technologies, Inc.

Chinnakrishnan Ballapuram

Taeksang Song

Saira Samar Malik

Kang-Yong Kim

Hyunyoo Lee

Kimberly Judy Lobo

Akhila Gundu

Shay Benisty

Oscar Prem Pinto

Wentao Wu

Robert Brennan

Anand Subramanian

Ajay Sundar Raj

A non-volatile storage system includes: a host and a storage device. The host includes a submission queue memory, a completion queue memory, and a read/write data memory, and the storage device includes: a controller configured to concurrently communicate with the read/write data memory and with at least one of the submission queue memory and the completion queue memory; and a memory device configured to communicate with the controller.

Systems and methods for servicing data access commands

Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.

Techniques for partial writes

Methods, systems, and devices for an efficient turnaround policy for a bus are described. A device may include a memory and a bus for communicating with the memory. The device may operate the bus in a first direction, relative to the memory, that is associated with a first type of access command. The device may determine, for the memory, that a quantity of queued access commands of a second type are for one or more banks that have satisfied a timing constraint for activating different rows in a same bank. Based on determining that the quantity of queued access commands of the second type are for one or more banks that have satisfied the timing constraint, the device may operate the bus in a second direction, relative to the memory, that is associated with the second type of access command.

Efficient turnaround policy for a bus

Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

Centralized error correction circuit

Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.

Opportunistic data movement

Methods, systems, and devices for cache management in a memory subsystem are described. An interface controller may include a first buffer and a second buffer. The interface controller may use the first and second buffers to facilitate operating a volatile memory as a cache for a non-volatile memory. During an access operation, the interface controller may use the buffer to transfer data between the volatile memory, non-volatile memory, and another device. In response to the access operation, the interface controller may use the second buffer to transfer second data from the volatile memory to the non-volatile memory.

Cache management in a memory subsystem

A data storage device whose controller is configured to apply a hash function to a logical address specified in a received host request to obtain a first portion of the corresponding physical address (e.g., the channel number or channel and die numbers). This feature of the controller enables the L2P table stored in the DRAM associated with the controller to have physical-address entries that contain therein only complementary second portions of the physical addresses, but not the first portions. Such shorter physical-address entries in the L2P table enable a corresponding beneficial reduction in the size of the DRAM and can further be leveraged to have optimized and aligned access to the L2P table in the DRAM.

Relative size reduction of a logical-to-physical table

A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.

Machine learning for a multi-memory system

Methods, systems, and devices for strategic power mode transition in a multi-memory device are described. A controller may receive, from a host device, a command indicating that the controller is to transition a volatile memory and a non-volatile memory from respective deep sleep modes. In a first example, the controller may respond to the command by transitioning the volatile memory to a standby power mode for the volatile memory and transitioning the non-volatile memory to an intermediate power mode for the non-volatile memory that consumes less power than a standby mode for the non-volatile memory. In a second example, the controller may respond to the command by transitioning the volatile memory to the standby power mode for the volatile memory and maintain the non-volatile memory in the deep sleep mode until a condition, such as a miss, occurs.

Strategic power mode transition in a multi-memory device

Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.

Power mode control in a multi-memory device based on queue length

Methods, systems, and devices for scratchpad memory in a cache are described. A device may operate a portion of a volatile memory in a cache mode having non-deterministic latency for satisfying requests from a host device. The device may monitor a register with an output pin that is associated with the portion and indicative of an operating mode of the portion. Based on or in response to monitoring the output pin, the device may determine whether to change the operating mode of the portion from the cache mode to a scratchpad mode having deterministic latency for satisfying requests from the host device.

Scratchpad memory in a cache

Methods, systems, and devices for hazard detection in a multi-memory device are described. A device may receive a first command that indicates a first bank address, a first row address, and a first column address. Based on the first bank address, the device may select a buffer for a hazard detection procedure that detects hazardous commands. The device may compare, as part of the hazard detection procedure, the first row address and the first column address from the first command with a second row address and a second column address from a second command in the buffer. The device may determine whether the first command and the second command are hazardous commands based on comparing the first row address and the first column address from the first command with the second row address and the second column address from the second command.

Hazard detection in a multi-memory device

Methods, systems, and devices for post error correction code (ECC) registers for cache metadata are described. A device may read metadata from a memory array included in the device. The metadata may include information for operating a volatile memory as a cache for a non-volatile memory. The device may perform an ECC operation on the metadata based on reading the metadata from the memory array. After performing the ECC operation on the metadata, the device may write the metadata to a register that is coupled with the memory array. The device may then write the metadata from the register to the memory array.

Post error correction code registers for cache metadata

Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

Memory wear management

Methods, systems, and devices for transaction management using metadata are described. In some examples, a memory device may include a volatile memory, and a non-volatile memory, which may have different access latencies. The memory device may receive from a host device a read command for data located at an address of the non-volatile memory. In response to the read command, the memory device and may determine whether the data is stored in the volatile memory. The memory device may then transmit, to the host device data and according to an expected latency, a set of data and an indication of whether the set of data was previously requested by the host device or unrequested by the host device. In some examples, the memory device may also transmit an identifier associated with the read command and a hash of the address.

Growing community of inventors

San Jose, CA, United States of America

Chinnakrishnan Ballapuram