Intel Corporation

Chinna B Prudvi

Derek T Bachand

David Lawrence Hill

Paul D Breuder

Matthew A Fisch

Deborah T Marr

David W Grawrock

Robert J Greiner

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Jay Joseph Nejedlo

Lyle E Cool

Brent E Lince

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Yuen Tat Lee

Wee Hoo Cheah

Arun R Ramadorai

Harish Kumar

Kapila B Udawatta

John L Baudrexl

Kip C Killpack

Loren James McConnell

Kyle Markley

Christian E Iovin

Sanjay S Salem

Evan J Halprin

David C Florey

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Quinn W Merrill

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Travis K Goff

Padmakumar Gopal

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.

Transaction manager and cache for processing agent

A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.

Dynamic priority external transaction system

Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

Method and apparatus for altering data length to zero to maintain cache coherency

A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.

Prefetch queue

An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.

Error correction system in a processing agent having minimal delay

A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a pending external transaction, canceling and recycling the data request.

Recycle mechanism for a processing agent

A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled &ldquo;SLIME.&rdquo; The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status. The data eviction method includes storing data in a cache, storing a status field in association with the data, the status field having a first sub-field to indicate whether the data is dirty and a second sub-field to indicate whether the data is shared, when the data is to be evicted from the cache, testing the first sub-field field to determine whether the data is dirty and, if so, writing the data to another cache before evicting the data from the cache. The multi-layer cache system includes first and second caches provided in a layered arrangement with the second cache being in a higher layer than the first cache, each cache including cache entries adapted to store data and status fields associated with the data, the status field representing the state of the data, eviction logic in the first cache adapted to test the status field of a cache entry, and control logic adapted to output the contents of the cache entry to a cache entry in the second cache when the status field indicates that data in the cache entry is dirty.

&ldquo;SLIME&rdquo; cache coherency system for agents with multi-layer caches

Prefetch queue responsive to read request sequences

Growing community of inventors

Portland, OR, United States of America

Chinna B Prudvi