Nxp B.v.

Chinmayee Kumari Panigrahi

Marcin Grad

Dolphin Abessolo Bidzo

Paul Hendrik Cappon

Maciej Skrobacki

Sunil Chandra Kasanyal

Shashank Sunil Amati

Aman Chugh

A communications circuit includes transmitter circuitry for driving a differential signal on two die terminal. The transmitter circuitry includes two drive transistors who conductivity is controlled to provide a path from a common node to each of the die terminals. A string of one or more diodes is coupled to the common node to provide a path for discharging ESD current from the common node from an ESD event affecting either die terminal.

Differential transmitter circuitry with ESD circuitry

A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

Level shifter with GIDL current reduction

A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.

Power down signal generator

An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

ESD protection circuit with GIDL current detection

A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.

Growing community of inventors

Bengaluru, India

Chinmayee Kumari Panigrahi