General Instrument Corporation

Microchip Technology Inc.

Conexant Systems, Inc.

General Instrument Corporation of Delaware

Artisan Components, Inc.

Nurlogic Design, Inc.

Chinh Luong Hoang

Michael J Brunolli

Paul N Katz

Robert C Gilberg

Burcin Serter Ergun

James E Smith

There is provided a demodulator system comprising a first input to receive a first analog signal at a first rate; a second input to receive a second analog signal at the first rate; a MUX coupled to the first input and the second input to receive the first analog signal and the second analog signal, and to multiplex the first analog signal and the second analog signal to generate a multiplexed analog output; an ADC to receive the multiplexed analog output and generate a multiplexed digital output, the ADC operating at a second rate, the second rate substantially equal to the first rate multiplied by a total number of input analog signals; a DEMUX to receive the multiplexed digital output and generate a first digital output having a first bitstream and a second digital output having a second bitstream corresponding to the first analog signal and the second analog signal.

System and method providing channel multiplexing for analog-to-digital conversion

A data signaling apparatus includes a differential amplifier for providing an amplified differential output on a pair of outputs in response to a differential signal provided on a pair of inputs, and a clamping resistor between the pair of inputs. The clamping resistor acts to effectively reduce the swing in differential inputs, thereby allowing high gain that does not result in problematic differential outputs. Further, since the resistor is operative for all voltage ranges, it is useful in small signal applications where diodes cannot be used or are too difficult to implement. A data signaling method includes receiving a differential signal on a pair of inputs, reducing the magnitude of the differential signal by a scale factor using a clamping resistor across the pair of inputs, and providing an amplified differential output on a pair of outputs in response to the scaled differential signal provided on the pair of inputs.

Method and apparatus for voltage clamping in feedback amplifiers using resistors

A low voltage differential signaling receiver includes a gain compensation and control circuit having a low common mode compensation circuit and a high common mode compensation circuit. A control circuit is coupled to both compensation circuits and senses the operation of one to control the operation of the other. The operation of the compensation circuits ensures that differential signals having a wide range of common mode input voltages are accurately detected by the receiver. The control circuit serves to keep the combined operation of the compensation circuits stable over the wide range of common mode input voltages.

Method and apparatus for gain compensation and control in low voltage differential signaling applications

A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

Digitally switched impedance having improved linearity and settling time

A digitally switched potentiometer has improved linearity by minimizing the amount of resistive error introduced by switches used to switch the resistive elements comprising the potentiometer. Improved settling time of the potentiometer is achieved by reducing the amount of switch capacitance connected to the output of the potentiometer. The digitally switched potentiometer may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of resistors needed for a desired number of resistive step changes is reduced by using two major resistor ranks and one minor resistor rank, or two minor resistor ranks and one major resistor rank connected in series.

Digitally switched potentiometer having improved linearity and settling time

Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Transistor circuit with transistor characteristic sensor

A power-out reset circuit includes reference voltage and current generators to generate a reference voltage and a reference current which are essentially independent of temperature variations over a useful temperature range, a delay/disable circuit, over and under voltage detectors and output logic circuitry. This circuit detects when the voltage level of a supply voltage source (+VDD) exceeds preselected limits. The reference voltage, which is related to the silicon band gap voltage, is connected to a first input of a comparator of each of the voltage detectors. The reference current, which is derived from the silicon band gap voltage, is connected to a current source of each of the detectors. Each detector has a hysteresis circuit which changes the point at which the comparator switches in the event that +VDD crosses into or outside of a preselected operating range. The delay/disable circuit ensures that the reference voltage is stable before the voltage detectors are activated, and that the voltage detectors are disabled when the supply voltage source falls below a minimum value which causes the reference voltage to be invalid (i.e., to be outside the preselected operating range. Outputs of the comparators are coupled to the output logic circuitry. The output logic circuitry includes a two input EXCLUSIVE OR logic circuit, a delay circuit, a two input OR logic gate, a transistor, a two input NOR logic gate, and an inverter.

Power-out reset system

An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency. The digital gate signals are stored in a non-volatile memory so that the oscillator will continue to operate at the adjusted frequency (i.e., that of the reference clock) even if the reference clock is no longer present and power is temporarily removed. The oscillator system is well suited for implementation by complementary metal oxide semiconductor (CMOS) technology as part of an integrated circuit (IC).

Ring oscillator with frequency control loop

Counting and division circuits include an input differential stage connected to a cross-coupled differential stage. The input stage includes first and second IGFETS whose gate electrodes are respectively connected to first and second inputs, whose drains are respectively connected to first and second outputs, and whose sources are connected to the drain of a third IGFET whose source is grounded. The cross-coupled stage includes fourth and fifth IGFETs which are cross-coupled in that the gate of the fourth IGFET and the drain of the fifth IGFET are directly connected to the first output and the gate of the fifth IGFET and the drain of the fourth IGFET are directly connected to the second output. The sources of the fourth and fifth IGFETs are connected in common to the drain of a sixth IGFET whose source is grounded. Control signals are applied to the gates of the third and sixth IGFETS for selectively and alternately turning them on one at a time and, simultaneously, setting the level of the current flowing through the differentially connected IGFETS in their drain circuit.

Current mode logic circuits employing IGFETS

An integrated circuit chip includes a secure memory element that stores secret data, an opaque layer of material encapsulating the chip, and means for eliminating the secret data from the secure memory element in the event that the encapsulation material is removed from the chip. The eliminating means comprise a protective circuit encapsulated by the encapsulation material and coupled to the secure memory element. The protective circuit incldues a light sensitive element having a current characteristic that has a detectable change upon exposure to light; means for detecting said current change when the light sensitive element is exposed to light; and switching means coupled to the secure memory element and the detecting means for causing the secret data to be removed from the secure memory element in response to said current change produced by the light sensitive element when the light sensitive element is exposed to light, such that should the encapsulation material be removed from the chip, the secret data is eliminated from the memory element.

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San Diego, CA, United States of America

Chinh Luong Hoang